From e98c61e9f33d3ab8d07f950af3f248554ac2d835 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 29 Apr 2021 11:51:14 +0200 Subject: [PATCH] radv: fix fast clearing DCC if one level can't be compressed on GFX10+ Fallback to a slow clear, this could be improved by splitting the clear into two parts (one fast and one slow) but that's complicated. Cc: 21.1 mesa-stable Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_meta_clear.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index d9c09e01682..b2f2864ebe9 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1521,18 +1521,25 @@ radv_can_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, const struct radv_ return false; } - if (iview->image->info.levels > 1 && - cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) { - for (uint32_t l = 0; l < iview->level_count; l++) { - uint32_t level = iview->base_mip + l; - struct legacy_surf_dcc_level *dcc_level = - &iview->image->planes[0].surface.u.legacy.color.dcc_level[level]; - - /* Do not fast clears if one level can't be - * fast cleared. - */ - if (!dcc_level->dcc_fast_clear_size) + if (iview->image->info.levels > 1) { + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + uint32_t last_level = iview->base_mip + iview->level_count - 1; + if (last_level >= iview->image->planes[0].surface.num_meta_levels) { + /* Do not fast clears if one level can't be fast cleard. */ return false; + } + } else { + for (uint32_t l = 0; l < iview->level_count; l++) { + uint32_t level = iview->base_mip + l; + struct legacy_surf_dcc_level *dcc_level = + &iview->image->planes[0].surface.u.legacy.color.dcc_level[level]; + + /* Do not fast clears if one level can't be + * fast cleared. + */ + if (!dcc_level->dcc_fast_clear_size) + return false; + } } } }