From e887c4d07a4ad49d37ca4cfb1aab2810d6d4936f Mon Sep 17 00:00:00 2001
From: Daniel Almeida <daniel.almeida@collabora.com>
Date: Tue, 18 Jul 2023 09:19:20 -0300
Subject: [PATCH] nak: add support for nir_op_bitfield_reverse

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
---
 src/nouveau/compiler/nak_encode_sm75.rs | 11 +++++++++++
 src/nouveau/compiler/nak_from_nir.rs    |  8 ++++++++
 src/nouveau/compiler/nak_ir.rs          | 18 +++++++++++++++++-
 src/nouveau/compiler/nak_legalize.rs    |  3 ++-
 4 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/src/nouveau/compiler/nak_encode_sm75.rs b/src/nouveau/compiler/nak_encode_sm75.rs
index 67134572c2f..25be2d56e92 100644
--- a/src/nouveau/compiler/nak_encode_sm75.rs
+++ b/src/nouveau/compiler/nak_encode_sm75.rs
@@ -1494,6 +1494,16 @@ impl SM75Instr {
         self.set_field(63..64, not_mod)
     }
 
+    fn encode_brev(&mut self, op: &OpBrev) {
+        self.encode_alu(
+            0x101,
+            Some(op.dst),
+            ALUSrc::None,
+            ALUSrc::from_src(&op.src),
+            ALUSrc::None,
+        );
+    }
+
     pub fn encode(
         instr: &Instr,
         sm: u8,
@@ -1553,6 +1563,7 @@ impl SM75Instr {
             Op::Bar(op) => si.encode_bar(&op),
             Op::S2R(op) => si.encode_s2r(&op),
             Op::PopC(op) => si.encode_popc(&op),
+            Op::Brev(op) => si.encode_brev(&op),
             _ => panic!("Unhandled instruction"),
         }
 
diff --git a/src/nouveau/compiler/nak_from_nir.rs b/src/nouveau/compiler/nak_from_nir.rs
index 53e00277842..764895234ba 100644
--- a/src/nouveau/compiler/nak_from_nir.rs
+++ b/src/nouveau/compiler/nak_from_nir.rs
@@ -216,6 +216,14 @@ impl<'a> ShaderFromNir<'a> {
                 });
                 dst
             }
+            nir_op_bitfield_reverse => {
+                let dst = b.alloc_ssa(RegFile::GPR, 1);
+                b.push_op(OpBrev {
+                    dst: dst.into(),
+                    src: srcs[0],
+                });
+                dst
+            }
             nir_op_f2i32 | nir_op_f2u32 => {
                 let src_bits = usize::from(alu.get_src(0).bit_size());
                 let dst_bits = alu.def.bit_size();
diff --git a/src/nouveau/compiler/nak_ir.rs b/src/nouveau/compiler/nak_ir.rs
index beb9e10410a..48d58082d1f 100644
--- a/src/nouveau/compiler/nak_ir.rs
+++ b/src/nouveau/compiler/nak_ir.rs
@@ -3150,6 +3150,21 @@ impl fmt::Display for OpPopC {
     }
 }
 
+#[repr(C)]
+#[derive(SrcsAsSlice, DstsAsSlice)]
+pub struct OpBrev {
+    pub dst: Dst,
+
+    #[src_type(ALU)]
+    pub src: Src,
+}
+
+impl fmt::Display for OpBrev {
+    fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
+        write!(f, "BREV {} {}", self.dst, self.src,)
+    }
+}
+
 #[derive(Display, DstsAsSlice, SrcsAsSlice, FromVariants)]
 pub enum Op {
     FAdd(OpFAdd),
@@ -3205,6 +3220,7 @@ pub enum Op {
     ParCopy(OpParCopy),
     FSOut(OpFSOut),
     PopC(OpPopC),
+    Brev(OpBrev),
 }
 
 #[derive(Clone, Copy, Eq, Hash, PartialEq)]
@@ -3521,7 +3537,7 @@ impl Instr {
             | Op::FSOut(_) => {
                 panic!("Not a hardware opcode")
             }
-            Op::PopC(_) => Some(15),
+            Op::PopC(_) | Op::Brev(_) => Some(15),
         }
     }
 }
diff --git a/src/nouveau/compiler/nak_legalize.rs b/src/nouveau/compiler/nak_legalize.rs
index 2602de141bd..42e63e3e3fa 100644
--- a/src/nouveau/compiler/nak_legalize.rs
+++ b/src/nouveau/compiler/nak_legalize.rs
@@ -187,7 +187,8 @@ impl<'a> LegalizeInstr<'a> {
             | Op::I2F(_)
             | Op::Mov(_)
             | Op::FRnd(_)
-            | Op::PopC(_) => (),
+            | Op::PopC(_)
+            | Op::Brev(_) => (),
             Op::Sel(op) => {
                 let [ref mut src0, ref mut src1] = op.srcs;
                 if !src_is_reg(src0) && src_is_reg(src1) {