From e83bd87ee94c04a62977c83d4e88f6a151109056 Mon Sep 17 00:00:00 2001 From: Konstantin Seurer Date: Fri, 24 Jun 2022 21:28:01 +0200 Subject: [PATCH] radv: Use nir_test_mask instead of i2b(iand) Signed-off-by: Konstantin Seurer Reviewed-by: Jason Ekstrand Part-of: --- src/amd/vulkan/radv_meta_etc_decode.c | 8 ++-- src/amd/vulkan/radv_nir_lower_abi.c | 3 +- src/amd/vulkan/radv_nir_lower_ray_queries.c | 28 ++++++-------- src/amd/vulkan/radv_pipeline_rt.c | 43 ++++++++------------- src/amd/vulkan/radv_query.c | 34 +++++++--------- src/amd/vulkan/radv_rt_common.c | 17 ++++---- 6 files changed, 53 insertions(+), 80 deletions(-) diff --git a/src/amd/vulkan/radv_meta_etc_decode.c b/src/amd/vulkan/radv_meta_etc_decode.c index 958c1219a46..ad7f8cbc2a5 100644 --- a/src/amd/vulkan/radv_meta_etc_decode.c +++ b/src/amd/vulkan/radv_meta_etc_decode.c @@ -273,7 +273,7 @@ build_shader(struct radv_device *dev) color_payload = flip_endian(&b, color_payload, 2); nir_ssa_def *color_y = nir_channel(&b, color_payload, 0); nir_ssa_def *color_x = nir_channel(&b, color_payload, 1); - nir_ssa_def *flip = nir_ine_imm(&b, nir_iand_imm(&b, color_y, 1), 0); + nir_ssa_def *flip = nir_test_mask(&b, color_y, 1); nir_ssa_def *subblock = nir_ushr_imm( &b, nir_bcsel(&b, flip, nir_channel(&b, pixel_coord, 1), nir_channel(&b, pixel_coord, 0)), 1); @@ -281,7 +281,7 @@ build_shader(struct radv_device *dev) nir_variable *punchthrough = nir_variable_create(b.shader, nir_var_shader_temp, glsl_bool_type(), "punchthrough"); nir_ssa_def *punchthrough_init = - nir_iand(&b, alpha_bits_1, nir_ieq_imm(&b, nir_iand_imm(&b, color_y, 2), 0)); + nir_iand(&b, alpha_bits_1, nir_inot(&b, nir_test_mask(&b, color_y, 2))); nir_store_var(&b, punchthrough, punchthrough_init, 0x1); nir_variable *etc1_compat = @@ -313,8 +313,8 @@ build_shader(struct radv_device *dev) nir_iand_imm(&b, nir_ushr(&b, color_x, nir_iadd_imm(&b, linear_pixel, 15)), 2); nir_ssa_def *lsb = nir_iand_imm(&b, nir_ushr(&b, color_x, linear_pixel), 1); - nir_push_if(&b, nir_iand(&b, nir_inot(&b, alpha_bits_1), - nir_ieq_imm(&b, nir_iand_imm(&b, color_y, 2), 0))); + nir_push_if( + &b, nir_iand(&b, nir_inot(&b, alpha_bits_1), nir_inot(&b, nir_test_mask(&b, color_y, 2)))); { nir_store_var(&b, etc1_compat, nir_imm_bool(&b, true), 1); nir_ssa_def *tmp[3]; diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c index 0cd9fece947..f23c70b7213 100644 --- a/src/amd/vulkan/radv_nir_lower_abi.c +++ b/src/amd/vulkan/radv_nir_lower_abi.c @@ -54,8 +54,7 @@ static nir_ssa_def * nggc_bool_setting(nir_builder *b, unsigned mask, lower_abi_state *s) { nir_ssa_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->ngg_culling_settings); - nir_ssa_def *x = nir_iand_imm(b, settings, mask); - return nir_ine(b, x, nir_imm_int(b, 0)); + return nir_test_mask(b, settings, mask); } static nir_ssa_def * diff --git a/src/amd/vulkan/radv_nir_lower_ray_queries.c b/src/amd/vulkan/radv_nir_lower_ray_queries.c index 084c6a83d55..f5ef445d8dc 100644 --- a/src/amd/vulkan/radv_nir_lower_ray_queries.c +++ b/src/amd/vulkan/radv_nir_lower_ray_queries.c @@ -298,9 +298,8 @@ static void insert_terminate_on_first_hit(nir_builder *b, nir_ssa_def *index, struct ray_query_vars *vars, bool break_on_terminate) { - nir_ssa_def *terminate_on_first_hit = nir_ine_imm( - b, nir_iand_imm(b, rq_load_var(b, index, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask), - 0); + nir_ssa_def *terminate_on_first_hit = + nir_test_mask(b, rq_load_var(b, index, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask); nir_push_if(b, terminate_on_first_hit); { rq_store_var(b, index, vars->incomplete, nir_imm_bool(b, false), 0x1); @@ -512,15 +511,13 @@ insert_traversal_triangle_case(struct radv_device *device, nir_builder *b, nir_s dist = nir_fdiv(b, dist, div); nir_ssa_def *frontface = nir_flt(b, nir_imm_float(b, 0), div); nir_ssa_def *switch_ccw = - nir_ine_imm(b, - nir_iand_imm(b, rq_load_var(b, index, vars->candidate.sbt_offset_and_flags), - VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR << 24), - 0); + nir_test_mask(b, rq_load_var(b, index, vars->candidate.sbt_offset_and_flags), + VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR << 24); frontface = nir_ixor(b, frontface, switch_ccw); rq_store_var(b, index, vars->candidate.frontface, frontface, 0x1); - nir_ssa_def *not_cull = nir_ieq_imm( - b, nir_iand_imm(b, rq_load_var(b, index, vars->flags), SpvRayFlagsSkipTrianglesKHRMask), 0); + nir_ssa_def *not_cull = nir_inot( + b, nir_test_mask(b, rq_load_var(b, index, vars->flags), SpvRayFlagsSkipTrianglesKHRMask)); nir_ssa_def *not_facing_cull = nir_ieq_imm( b, nir_iand(b, rq_load_var(b, index, vars->flags), @@ -530,12 +527,9 @@ insert_traversal_triangle_case(struct radv_device *device, nir_builder *b, nir_s not_cull = nir_iand( b, not_cull, - nir_ior( - b, not_facing_cull, - nir_ine_imm(b, - nir_iand_imm(b, rq_load_var(b, index, vars->candidate.sbt_offset_and_flags), - VK_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT_KHR << 24), - 0))); + nir_ior(b, not_facing_cull, + nir_test_mask(b, rq_load_var(b, index, vars->candidate.sbt_offset_and_flags), + VK_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT_KHR << 24))); nir_push_if(b, nir_iand(b, nir_iand(b, nir_fge(b, rq_load_var(b, index, vars->closest.t), dist), @@ -599,8 +593,8 @@ insert_traversal_aabb_case(struct radv_device *device, nir_builder *b, nir_ssa_d hit_is_opaque(b, rq_load_var(b, index, vars->candidate.sbt_offset_and_flags), rq_load_var(b, index, vars->flags), geometry_id_and_flags); - nir_ssa_def *not_skip_aabb = nir_ieq_imm( - b, nir_iand_imm(b, rq_load_var(b, index, vars->flags), SpvRayFlagsSkipAABBsKHRMask), 0); + nir_ssa_def *not_skip_aabb = nir_inot( + b, nir_test_mask(b, rq_load_var(b, index, vars->flags), SpvRayFlagsSkipAABBsKHRMask)); nir_ssa_def *not_cull = nir_iand( b, not_skip_aabb, nir_ieq_imm(b, diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c index a61a073f607..0b79318ef02 100644 --- a/src/amd/vulkan/radv_pipeline_rt.c +++ b/src/amd/vulkan/radv_pipeline_rt.c @@ -1128,14 +1128,12 @@ insert_traversal_triangle_case(struct radv_device *device, dist = nir_fdiv(b, dist, div); nir_ssa_def *frontface = nir_flt(b, nir_imm_float(b, 0), div); nir_ssa_def *switch_ccw = - nir_ine_imm(b, - nir_iand_imm(b, nir_load_var(b, trav_vars->sbt_offset_and_flags), - VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR << 24), - 0); + nir_test_mask(b, nir_load_var(b, trav_vars->sbt_offset_and_flags), + VK_GEOMETRY_INSTANCE_TRIANGLE_FRONT_COUNTERCLOCKWISE_BIT_KHR << 24); frontface = nir_ixor(b, frontface, switch_ccw); - nir_ssa_def *not_cull = nir_ieq_imm( - b, nir_iand_imm(b, nir_load_var(b, vars->flags), SpvRayFlagsSkipTrianglesKHRMask), 0); + nir_ssa_def *not_cull = + nir_inot(b, nir_test_mask(b, nir_load_var(b, vars->flags), SpvRayFlagsSkipTrianglesKHRMask)); nir_ssa_def *not_facing_cull = nir_ieq_imm( b, nir_iand(b, nir_load_var(b, vars->flags), @@ -1145,12 +1143,9 @@ insert_traversal_triangle_case(struct radv_device *device, not_cull = nir_iand( b, not_cull, - nir_ior( - b, not_facing_cull, - nir_ine_imm(b, - nir_iand_imm(b, nir_load_var(b, trav_vars->sbt_offset_and_flags), - VK_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT_KHR << 24), - 0))); + nir_ior(b, not_facing_cull, + nir_test_mask(b, nir_load_var(b, trav_vars->sbt_offset_and_flags), + VK_GEOMETRY_INSTANCE_TRIANGLE_FACING_CULL_DISABLE_BIT_KHR << 24))); nir_push_if(b, nir_iand(b, nir_iand(b, nir_flt(b, dist, nir_load_var(b, vars->tmax)), @@ -1232,16 +1227,13 @@ insert_traversal_triangle_case(struct radv_device *device, nir_store_var(b, trav_vars->should_return, nir_ior(b, - nir_ine_imm(b, - nir_iand_imm(b, nir_load_var(b, vars->flags), - SpvRayFlagsSkipClosestHitShaderKHRMask), - 0), + nir_test_mask(b, nir_load_var(b, vars->flags), + SpvRayFlagsSkipClosestHitShaderKHRMask), nir_ieq_imm(b, nir_load_var(b, vars->idx), 0)), 1); - nir_ssa_def *terminate_on_first_hit = nir_ine_imm( - b, nir_iand_imm(b, nir_load_var(b, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask), - 0); + nir_ssa_def *terminate_on_first_hit = + nir_test_mask(b, nir_load_var(b, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask); nir_ssa_def *ray_terminated = nir_ieq_imm(b, nir_load_var(b, vars->ahit_status), rt_ahit_status_terminate); nir_push_if(b, nir_ior(b, terminate_on_first_hit, ray_terminated)); @@ -1270,7 +1262,7 @@ insert_traversal_aabb_case(struct radv_device *device, nir_load_var(b, vars->flags), geometry_id_and_flags); nir_ssa_def *not_skip_aabb = - nir_ieq_imm(b, nir_iand_imm(b, nir_load_var(b, vars->flags), SpvRayFlagsSkipAABBsKHRMask), 0); + nir_inot(b, nir_test_mask(b, nir_load_var(b, vars->flags), SpvRayFlagsSkipAABBsKHRMask)); nir_ssa_def *not_cull = nir_iand( b, not_skip_aabb, nir_ieq_imm(b, @@ -1386,16 +1378,13 @@ insert_traversal_aabb_case(struct radv_device *device, nir_store_var(b, trav_vars->should_return, nir_ior(b, - nir_ine_imm(b, - nir_iand_imm(b, nir_load_var(b, vars->flags), - SpvRayFlagsSkipClosestHitShaderKHRMask), - 0), + nir_test_mask(b, nir_load_var(b, vars->flags), + SpvRayFlagsSkipClosestHitShaderKHRMask), nir_ieq_imm(b, nir_load_var(b, vars->idx), 0)), 1); - nir_ssa_def *terminate_on_first_hit = nir_ine_imm( - b, nir_iand_imm(b, nir_load_var(b, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask), - 0); + nir_ssa_def *terminate_on_first_hit = + nir_test_mask(b, nir_load_var(b, vars->flags), SpvRayFlagsTerminateOnFirstHitKHRMask); nir_ssa_def *ray_terminated = nir_ieq_imm(b, nir_load_var(b, vars->ahit_status), rt_ahit_status_terminate); nir_push_if(b, nir_ior(b, terminate_on_first_hit, ray_terminated)); diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 63053f26fbb..d897e8103a5 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -41,19 +41,13 @@ static const int pipelinestat_block_size = 11 * 8; static const unsigned pipeline_statistics_indices[] = {7, 6, 3, 4, 5, 2, 1, 0, 8, 9, 10}; -static nir_ssa_def * -nir_test_flag(nir_builder *b, nir_ssa_def *flags, uint32_t flag) -{ - return nir_i2b(b, nir_iand_imm(b, flags, flag)); -} - static void radv_store_availability(nir_builder *b, nir_ssa_def *flags, nir_ssa_def *dst_buf, nir_ssa_def *offset, nir_ssa_def *value32) { - nir_push_if(b, nir_test_flag(b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)); + nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)); - nir_push_if(b, nir_test_flag(b, flags, VK_QUERY_RESULT_64_BIT)); + nir_push_if(b, nir_test_mask(b, flags, VK_QUERY_RESULT_64_BIT)); nir_store_ssbo(b, nir_vec2(b, value32, nir_imm_int(b, 0)), dst_buf, offset, .align_mul = 8); @@ -174,10 +168,10 @@ build_occlusion_query_shader(struct radv_device *device) /* Store the result if complete or if partial results have been requested. */ - nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT); + nir_ssa_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4)); - nir_push_if(&b, nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), + nir_push_if(&b, nir_ior(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), nir_load_var(&b, available))); nir_push_if(&b, result_is_64bit); @@ -280,7 +274,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device) nir_ssa_def *available32 = nir_load_ssbo(&b, 1, 32, src_buf, avail_offset); - nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT); + nir_ssa_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); nir_ssa_def *elem_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4)); nir_ssa_def *elem_count = nir_ushr_imm(&b, stats_mask, 16); @@ -292,7 +286,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device) nir_store_var(&b, output_offset, output_base, 0x1); for (int i = 0; i < ARRAY_SIZE(pipeline_statistics_indices); ++i) { - nir_push_if(&b, nir_test_flag(&b, stats_mask, 1u << i)); + nir_push_if(&b, nir_test_mask(&b, stats_mask, BITFIELD64_BIT(i))); nir_ssa_def *start_offset = nir_iadd_imm(&b, input_base, pipeline_statistics_indices[i] * 8); nir_ssa_def *start = nir_load_ssbo(&b, 1, 64, src_buf, start_offset); @@ -341,7 +335,7 @@ build_pipeline_statistics_query_shader(struct radv_device *device) nir_push_else(&b, NULL); /* nir_i2b(&b, available32) */ - nir_push_if(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT)); + nir_push_if(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT)); /* Stores zeros in all outputs. */ @@ -444,7 +438,7 @@ build_tfb_query_shader(struct radv_device *device) avails[0] = nir_iand(&b, nir_channel(&b, load1, 1), nir_channel(&b, load1, 3)); avails[1] = nir_iand(&b, nir_channel(&b, load2, 1), nir_channel(&b, load2, 3)); nir_ssa_def *result_is_available = - nir_i2b(&b, nir_iand_imm(&b, nir_iand(&b, avails[0], avails[1]), 0x80000000)); + nir_test_mask(&b, nir_iand(&b, avails[0], avails[1]), 0x80000000); /* Only compute result if available. */ nir_push_if(&b, result_is_available); @@ -470,12 +464,12 @@ build_tfb_query_shader(struct radv_device *device) nir_pop_if(&b, NULL); /* Determine if result is 64 or 32 bit. */ - nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT); + nir_ssa_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 16), nir_imm_int(&b, 8)); /* Store the result if complete or partial results have been requested. */ - nir_push_if(&b, nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), + nir_push_if(&b, nir_ior(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), nir_load_var(&b, available))); /* Store result. */ @@ -574,12 +568,12 @@ build_timestamp_query_shader(struct radv_device *device) nir_pop_if(&b, NULL); /* Determine if result is 64 or 32 bit. */ - nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT); + nir_ssa_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 8), nir_imm_int(&b, 4)); /* Store the result if complete or partial results have been requested. */ - nir_push_if(&b, nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), + nir_push_if(&b, nir_ior(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), nir_load_var(&b, available))); /* Store result. */ @@ -723,12 +717,12 @@ build_pg_query_shader(struct radv_device *device) nir_pop_if(&b, NULL); /* Determine if result is 64 or 32 bit. */ - nir_ssa_def *result_is_64bit = nir_test_flag(&b, flags, VK_QUERY_RESULT_64_BIT); + nir_ssa_def *result_is_64bit = nir_test_mask(&b, flags, VK_QUERY_RESULT_64_BIT); nir_ssa_def *result_size = nir_bcsel(&b, result_is_64bit, nir_imm_int(&b, 16), nir_imm_int(&b, 8)); /* Store the result if complete or partial results have been requested. */ - nir_push_if(&b, nir_ior(&b, nir_test_flag(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), + nir_push_if(&b, nir_ior(&b, nir_test_mask(&b, flags, VK_QUERY_RESULT_PARTIAL_BIT), nir_load_var(&b, available))); /* Store result. */ diff --git a/src/amd/vulkan/radv_rt_common.c b/src/amd/vulkan/radv_rt_common.c index e44c4f5ba0f..58903d068ab 100644 --- a/src/amd/vulkan/radv_rt_common.c +++ b/src/amd/vulkan/radv_rt_common.c @@ -404,21 +404,18 @@ hit_is_opaque(nir_builder *b, nir_ssa_def *sbt_offset_and_flags, nir_ssa_def *fl nir_ssa_def *geometry_id_and_flags) { nir_ssa_def *geom_force_opaque = - nir_ine_imm(b, nir_iand_imm(b, geometry_id_and_flags, VK_GEOMETRY_OPAQUE_BIT_KHR << 28), 0); - nir_ssa_def *instance_force_opaque = nir_ine_imm( - b, nir_iand_imm(b, sbt_offset_and_flags, VK_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT_KHR << 24), 0); - nir_ssa_def *instance_force_non_opaque = nir_ine_imm( - b, nir_iand_imm(b, sbt_offset_and_flags, VK_GEOMETRY_INSTANCE_FORCE_NO_OPAQUE_BIT_KHR << 24), - 0); + nir_test_mask(b, geometry_id_and_flags, VK_GEOMETRY_OPAQUE_BIT_KHR << 28); + nir_ssa_def *instance_force_opaque = + nir_test_mask(b, sbt_offset_and_flags, VK_GEOMETRY_INSTANCE_FORCE_OPAQUE_BIT_KHR << 24); + nir_ssa_def *instance_force_non_opaque = + nir_test_mask(b, sbt_offset_and_flags, VK_GEOMETRY_INSTANCE_FORCE_NO_OPAQUE_BIT_KHR << 24); nir_ssa_def *opaque = geom_force_opaque; opaque = nir_bcsel(b, instance_force_opaque, nir_imm_bool(b, true), opaque); opaque = nir_bcsel(b, instance_force_non_opaque, nir_imm_bool(b, false), opaque); - nir_ssa_def *ray_force_opaque = - nir_ine_imm(b, nir_iand_imm(b, flags, SpvRayFlagsOpaqueKHRMask), 0); - nir_ssa_def *ray_force_non_opaque = - nir_ine_imm(b, nir_iand_imm(b, flags, SpvRayFlagsNoOpaqueKHRMask), 0); + nir_ssa_def *ray_force_opaque = nir_test_mask(b, flags, SpvRayFlagsOpaqueKHRMask); + nir_ssa_def *ray_force_non_opaque = nir_test_mask(b, flags, SpvRayFlagsNoOpaqueKHRMask); opaque = nir_bcsel(b, ray_force_opaque, nir_imm_bool(b, true), opaque); opaque = nir_bcsel(b, ray_force_non_opaque, nir_imm_bool(b, false), opaque);