From e7ed7a32cd58dc80a3882a1aa6b1f080cac9f96b Mon Sep 17 00:00:00 2001
From: Connor Abbott <cwabbott0@gmail.com>
Date: Tue, 19 Dec 2023 20:06:06 -0500
Subject: [PATCH] freedreno/afuc: Add a7xx test case

This tests new instructions, alignment, and sections.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26771>
---
 .../.gitlab-ci/reference/afuc_test_a7xx.asm   | 645 ++++++++++++++++
 .../.gitlab-ci/reference/afuc_test_a7xx.fw    | Bin 0 -> 2408 bytes
 .../.gitlab-ci/traces/afuc_test_a7xx.asm      | 725 ++++++++++++++++++
 src/freedreno/afuc/meson.build                |  21 +
 4 files changed, 1391 insertions(+)
 create mode 100644 src/freedreno/.gitlab-ci/reference/afuc_test_a7xx.asm
 create mode 100644 src/freedreno/.gitlab-ci/reference/afuc_test_a7xx.fw
 create mode 100644 src/freedreno/.gitlab-ci/traces/afuc_test_a7xx.asm

diff --git a/src/freedreno/.gitlab-ci/reference/afuc_test_a7xx.asm b/src/freedreno/.gitlab-ci/reference/afuc_test_a7xx.asm
new file mode 100644
index 00000000000..c67f2e02ff2
--- /dev/null
+++ b/src/freedreno/.gitlab-ci/reference/afuc_test_a7xx.asm
@@ -0,0 +1,645 @@
+; a7xx microcode
+; Version: 01000001
+
+[01000001]
+[#jumptbl]
+mov $01, 0x830	; CP_SQE_INSTR_BASE
+mov $02, 0x2
+cwrite $01, [$00 + @REG_READ_ADDR]
+cwrite $02, [$00 + @REG_READ_DWORDS]
+mov $01, $regdata
+mov $02, $regdata
+add $01, $01, 0x4
+addhi $02, $02, 0x0
+mov $03, 0x1
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $03, [$00 + @MEM_READ_DWORDS]
+rot $04, $memdata, 0x8
+ushr $04, $04, 0x6
+sub $04, $04, 0x4
+add $01, $01, $04
+addhi $02, $02, 0x0
+mov $rem, 0x80
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $02, [$00 + @LOAD_STORE_HI]
+cwrite $rem, [$00 + @MEM_READ_DWORDS]
+cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
+(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
+add $01, $01, 0x200
+addhi $02, $02, 0x0
+cwrite $01, [$00 + @BV_INSTR_BASE]
+cwrite $02, [$00 + @BV_INSTR_BASE+0x1]
+cwrite $03, [$00 + @BV_CNTL]
+add $01, $01, 0x4
+addhi $02, $02, 0x0
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $03, [$00 + @MEM_READ_DWORDS]
+rot $04, $memdata, 0x8
+ushr $04, $04, 0x6
+sub $04, $04, 0x4
+add $01, $01, $04
+addhi $02, $02, 0x0
+add $01, $01, 0x200
+addhi $02, $02, 0x0
+cwrite $01, [$00 + @LPAC_INSTR_BASE]
+cwrite $02, [$00 + @LPAC_INSTR_BASE+0x1]
+cwrite $03, [$00 + @LPAC_CNTL]
+mov $02, 0x883	; CP_SCRATCH[0].REG
+mov $03, 0xbeef
+mov $04, 0xdead << 16
+or $03, $03, $04
+cwrite $02, [$00 + @REG_WRITE_ADDR]
+cwrite $03, [$00 + @REG_WRITE]
+waitin
+mov $01, $data
+
+CP_ME_INIT:
+mov $02, 0x2
+waitin
+mov $01, $data
+
+CP_MEM_WRITE:
+mov $addr, 0xa0 << 24	; |NRT_ADDR
+mov $02, 0x4
+(xmov1)add $data, $02, $data
+mov $addr, 0xa204 << 16	; |NRT_DATA
+(rep)(xmov3)mov $data, $data
+waitin
+mov $01, $data
+
+UNKN76:
+mov $02, 0xff
+(rep)cwrite $data, [$02 + 0x1]!
+waitin
+mov $01, $data
+
+CP_SET_DRAW_STATE:
+(rep)(sds2)cwrite $data, [$00 + @DRAW_STATE_SET_HDR]
+waitin
+mov $01, $data
+
+CP_SET_BIN_DATA5:
+sread $02, [$00 + %SP]
+swrite $02, [$00 + %SP]
+mov $02, 0x7
+(rep)swrite $data, [$02 + 0x1]!
+waitin
+mov $01, $data
+
+CP_SET_SECURE_MODE:
+mov $02, $data
+setsecure $02, #l81
+l79:
+jump #l79
+nop
+l81:
+waitin
+mov $01, $data
+
+fxn83:
+l83:
+cmp $04, $02, $03
+breq $04, b0, #l90
+brne $04, b1, #l88
+breq $04, b2, #l83
+sub $03, $03, $02
+l88:
+jump #l83
+sub $02, $02, $03
+l90:
+ret
+nop
+
+CP_REG_RMW:
+cwrite $data, [$00 + @REG_READ_ADDR]
+add $02, $regdata, 0x42
+addhi $03, $00, $regdata
+sub $02, $02, $regdata
+call #fxn83
+subhi $03, $03, $regdata
+and $02, $02, $regdata
+or $02, $02, 0x1
+xor $02, $02, 0x1
+not $02, $02
+shl $02, $02, $regdata
+ushr $02, $02, $regdata
+ishr $02, $02, $regdata
+rot $02, $02, $regdata
+min $02, $02, $regdata
+max $02, $02, $regdata
+mul8 $02, $02, $regdata
+bic $02, $02, $regdata
+msb $02, $02
+bfi $02, $03, b1, b2
+setbit $02, $02, b3
+clrbit $02, $02, b4
+setbit $02, $02, $03
+ubfx $03, $02, b5, b6
+mov $usraddr, $data
+mov $data, $02
+(peek)mov $00, $data
+waitin
+mov $01, $data
+
+CP_MEMCPY:
+mov $02, $data
+mov $03, $data
+mov $04, $data
+mov $05, $data
+mov $06, $data
+l126:
+breq $06, 0x0, #l132
+cwrite $03, [$00 + @LOAD_STORE_HI]
+load $07, [$02 + 0x4]!
+cwrite $05, [$00 + @LOAD_STORE_HI]
+jump #l126
+store $07, [$04 + 0x4]!
+l132:
+waitin
+mov $01, $data
+
+CP_MEM_TO_MEM:
+cwrite $data, [$00 + @MEM_READ_ADDR]
+cwrite $data, [$00 + @MEM_READ_ADDR+0x1]
+mov $02, $data
+cwrite $data, [$00 + @LOAD_STORE_HI]
+mov $rem, $data
+cwrite $rem, [$00 + @MEM_READ_DWORDS]
+(rep)store $memdata, [$02 + 0x4]!
+waitin
+mov $01, $data
+
+IN_PREEMPT:
+cread $02, [$00 + 0x101]
+brne $02, 0x1, #l152
+nop
+preemptleave #l79
+nop
+nop
+nop
+waitin
+mov $01, $data
+l152:
+iret
+nop
+
+CP_BLIT:
+CP_BOOTSTRAP_UCODE:
+CP_BV_BR_COUNT_OPS:
+CP_COND_EXEC:
+CP_COND_INDIRECT_BUFFER_PFE:
+CP_COND_REG_EXEC:
+CP_COND_WRITE5:
+CP_CONTEXT_REG_BUNCH:
+CP_CONTEXT_REG_BUNCH2:
+CP_CONTEXT_SWITCH_YIELD:
+CP_CONTEXT_UPDATE:
+CP_DRAW_AUTO:
+CP_DRAW_INDIRECT:
+CP_DRAW_INDIRECT_MULTI:
+CP_DRAW_INDX:
+CP_DRAW_INDX_INDIRECT:
+CP_DRAW_INDX_OFFSET:
+CP_DRAW_PRED_ENABLE_GLOBAL:
+CP_DRAW_PRED_ENABLE_LOCAL:
+CP_DRAW_PRED_SET:
+CP_END_BIN:
+CP_EVENT_WRITE7:
+CP_EVENT_WRITE_CFL:
+CP_EVENT_WRITE_SHD:
+CP_EVENT_WRITE_ZPD:
+CP_EXEC_CS:
+CP_EXEC_CS_INDIRECT:
+CP_FIXED_STRIDE_DRAW_TABLE:
+CP_GLOBAL_TIMESTAMP:
+CP_IM_LOAD:
+CP_IM_LOAD_IMMEDIATE:
+CP_INDIRECT_BUFFER:
+CP_INDIRECT_BUFFER_CHAIN:
+CP_INDIRECT_BUFFER_PFD:
+CP_INTERRUPT:
+CP_INVALIDATE_STATE:
+CP_LOAD_STATE6:
+CP_LOAD_STATE6_FRAG:
+CP_LOAD_STATE6_GEOM:
+CP_LOCAL_TIMESTAMP:
+CP_MEM_TO_REG:
+CP_MEM_TO_SCRATCH_MEM:
+CP_MEM_WRITE_CNTR:
+CP_MODIFY_TIMESTAMP:
+CP_NOP:
+CP_RECORD_PFP_TIMESTAMP:
+CP_REG_TEST:
+CP_REG_TO_MEM:
+CP_REG_TO_MEM_OFFSET_MEM:
+CP_REG_TO_MEM_OFFSET_REG:
+CP_REG_TO_SCRATCH:
+CP_REG_WR_NO_CTXT:
+CP_RESET_CONTEXT_STATE:
+CP_RESOURCE_LIST:
+CP_RUN_OPENCL:
+CP_SCRATCH_TO_REG:
+CP_SET_BIN_DATA5_OFFSET:
+CP_SET_CTXSWITCH_IB:
+CP_SET_DRAW_INIT_FLAGS:
+CP_SET_MARKER:
+CP_SET_MODE:
+CP_SET_PROTECTED_MODE:
+CP_SET_PSEUDO_REG:
+CP_SET_STATE:
+CP_SET_SUBDRAW_SIZE:
+CP_SET_UNK_BIN_DATA:
+CP_SET_VISIBILITY_OVERRIDE:
+CP_SKIP_IB2_ENABLE_GLOBAL:
+CP_SKIP_IB2_ENABLE_LOCAL:
+CP_SMMU_TABLE_UPDATE:
+CP_START_BIN:
+CP_TEST_TWO_MEMS:
+CP_THREAD_CONTROL:
+CP_WAIT_FOR_IDLE:
+CP_WAIT_FOR_ME:
+CP_WAIT_MEM_WRITES:
+CP_WAIT_REG_EQ:
+CP_WAIT_REG_MEM:
+CP_WAIT_TIMESTAMP:
+CP_WHERE_AM_I:
+IN_GMU_INTERRUPT:
+IN_IB_END:
+PKT4:
+UNKN0:
+UNKN1:
+UNKN103:
+UNKN104:
+UNKN105:
+UNKN106:
+UNKN108:
+UNKN109:
+UNKN110:
+UNKN112:
+UNKN118:
+UNKN119:
+UNKN12:
+UNKN121:
+UNKN122:
+UNKN123:
+UNKN124:
+UNKN125:
+UNKN126:
+UNKN13:
+UNKN14:
+UNKN2:
+UNKN3:
+UNKN30:
+UNKN32:
+UNKN48:
+UNKN5:
+UNKN6:
+UNKN7:
+UNKN8:
+UNKN84:
+UNKN9:
+UNKN90:
+UNKN96:
+UNKN97:
+waitin
+mov $01, $data
+nop
+nop
+nop
+nop
+.align 32
+jumptbl:
+.jumptbl
+
+.section BV
+;
+; BV microcode:
+;
+[01000001]
+[#jumptbl]
+cread $01, [$00 + @BV_INSTR_BASE]
+cread $02, [$00 + @BV_INSTR_BASE+0x1]
+add $01, $01, 0x4
+addhi $02, $02, 0x0
+mov $03, 0x1
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $03, [$00 + @MEM_READ_DWORDS]
+rot $04, $memdata, 0x8
+ushr $04, $04, 0x6
+sub $04, $04, 0x4
+add $01, $01, $04
+addhi $02, $02, 0x0
+mov $rem, 0x80
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $02, [$00 + @LOAD_STORE_HI]
+cwrite $rem, [$00 + @MEM_READ_DWORDS]
+cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
+(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
+add $01, $01, 0x200
+addhi $02, $02, 0x0
+cwrite $01, [$00 + @LPAC_INSTR_BASE]
+cwrite $02, [$00 + @LPAC_INSTR_BASE+0x1]
+waitin
+mov $01, $data
+
+CP_BLIT:
+CP_BOOTSTRAP_UCODE:
+CP_BV_BR_COUNT_OPS:
+CP_COND_EXEC:
+CP_COND_INDIRECT_BUFFER_PFE:
+CP_COND_REG_EXEC:
+CP_COND_WRITE5:
+CP_CONTEXT_REG_BUNCH:
+CP_CONTEXT_REG_BUNCH2:
+CP_CONTEXT_SWITCH_YIELD:
+CP_CONTEXT_UPDATE:
+CP_DRAW_AUTO:
+CP_DRAW_INDIRECT:
+CP_DRAW_INDIRECT_MULTI:
+CP_DRAW_INDX:
+CP_DRAW_INDX_INDIRECT:
+CP_DRAW_INDX_OFFSET:
+CP_DRAW_PRED_ENABLE_GLOBAL:
+CP_DRAW_PRED_ENABLE_LOCAL:
+CP_DRAW_PRED_SET:
+CP_END_BIN:
+CP_EVENT_WRITE7:
+CP_EVENT_WRITE_CFL:
+CP_EVENT_WRITE_SHD:
+CP_EVENT_WRITE_ZPD:
+CP_EXEC_CS:
+CP_EXEC_CS_INDIRECT:
+CP_FIXED_STRIDE_DRAW_TABLE:
+CP_GLOBAL_TIMESTAMP:
+CP_IM_LOAD:
+CP_IM_LOAD_IMMEDIATE:
+CP_INDIRECT_BUFFER:
+CP_INDIRECT_BUFFER_CHAIN:
+CP_INDIRECT_BUFFER_PFD:
+CP_INTERRUPT:
+CP_INVALIDATE_STATE:
+CP_LOAD_STATE6:
+CP_LOAD_STATE6_FRAG:
+CP_LOAD_STATE6_GEOM:
+CP_LOCAL_TIMESTAMP:
+CP_MEMCPY:
+CP_MEM_TO_MEM:
+CP_MEM_TO_REG:
+CP_MEM_TO_SCRATCH_MEM:
+CP_MEM_WRITE:
+CP_MEM_WRITE_CNTR:
+CP_ME_INIT:
+CP_MODIFY_TIMESTAMP:
+CP_NOP:
+CP_RECORD_PFP_TIMESTAMP:
+CP_REG_RMW:
+CP_REG_TEST:
+CP_REG_TO_MEM:
+CP_REG_TO_MEM_OFFSET_MEM:
+CP_REG_TO_MEM_OFFSET_REG:
+CP_REG_TO_SCRATCH:
+CP_REG_WR_NO_CTXT:
+CP_RESET_CONTEXT_STATE:
+CP_RESOURCE_LIST:
+CP_RUN_OPENCL:
+CP_SCRATCH_TO_REG:
+CP_SET_BIN_DATA5:
+CP_SET_BIN_DATA5_OFFSET:
+CP_SET_CTXSWITCH_IB:
+CP_SET_DRAW_INIT_FLAGS:
+CP_SET_DRAW_STATE:
+CP_SET_MARKER:
+CP_SET_MODE:
+CP_SET_PROTECTED_MODE:
+CP_SET_PSEUDO_REG:
+CP_SET_SECURE_MODE:
+CP_SET_STATE:
+CP_SET_SUBDRAW_SIZE:
+CP_SET_UNK_BIN_DATA:
+CP_SET_VISIBILITY_OVERRIDE:
+CP_SKIP_IB2_ENABLE_GLOBAL:
+CP_SKIP_IB2_ENABLE_LOCAL:
+CP_SMMU_TABLE_UPDATE:
+CP_START_BIN:
+CP_TEST_TWO_MEMS:
+CP_THREAD_CONTROL:
+CP_WAIT_FOR_IDLE:
+CP_WAIT_FOR_ME:
+CP_WAIT_MEM_WRITES:
+CP_WAIT_REG_EQ:
+CP_WAIT_REG_MEM:
+CP_WAIT_TIMESTAMP:
+CP_WHERE_AM_I:
+IN_GMU_INTERRUPT:
+IN_IB_END:
+IN_PREEMPT:
+PKT4:
+UNKN0:
+UNKN1:
+UNKN103:
+UNKN104:
+UNKN105:
+UNKN106:
+UNKN108:
+UNKN109:
+UNKN110:
+UNKN112:
+UNKN118:
+UNKN119:
+UNKN12:
+UNKN121:
+UNKN122:
+UNKN123:
+UNKN124:
+UNKN125:
+UNKN126:
+UNKN13:
+UNKN14:
+UNKN2:
+UNKN3:
+UNKN30:
+UNKN32:
+UNKN48:
+UNKN5:
+UNKN6:
+UNKN7:
+UNKN76:
+UNKN8:
+UNKN84:
+UNKN9:
+UNKN90:
+UNKN96:
+UNKN97:
+waitin
+mov $01, $data
+nop
+nop
+.align 32
+jumptbl:
+.jumptbl
+
+.section LPAC
+;
+; LPAC microcode:
+;
+[01000001]
+[#jumptbl]
+cread $01, [$00 + @LPAC_INSTR_BASE]
+cread $02, [$00 + @LPAC_INSTR_BASE+0x1]
+add $01, $01, 0x4
+addhi $02, $02, 0x0
+mov $03, 0x1
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $03, [$00 + @MEM_READ_DWORDS]
+rot $04, $memdata, 0x8
+ushr $04, $04, 0x6
+sub $04, $04, 0x4
+add $01, $01, $04
+addhi $02, $02, 0x0
+mov $rem, 0x80
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $02, [$00 + @LOAD_STORE_HI]
+cwrite $rem, [$00 + @MEM_READ_DWORDS]
+cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
+(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
+
+CP_BLIT:
+CP_BOOTSTRAP_UCODE:
+CP_BV_BR_COUNT_OPS:
+CP_COND_EXEC:
+CP_COND_INDIRECT_BUFFER_PFE:
+CP_COND_REG_EXEC:
+CP_COND_WRITE5:
+CP_CONTEXT_REG_BUNCH:
+CP_CONTEXT_REG_BUNCH2:
+CP_CONTEXT_SWITCH_YIELD:
+CP_CONTEXT_UPDATE:
+CP_DRAW_AUTO:
+CP_DRAW_INDIRECT:
+CP_DRAW_INDIRECT_MULTI:
+CP_DRAW_INDX:
+CP_DRAW_INDX_INDIRECT:
+CP_DRAW_INDX_OFFSET:
+CP_DRAW_PRED_ENABLE_GLOBAL:
+CP_DRAW_PRED_ENABLE_LOCAL:
+CP_DRAW_PRED_SET:
+CP_END_BIN:
+CP_EVENT_WRITE7:
+CP_EVENT_WRITE_CFL:
+CP_EVENT_WRITE_SHD:
+CP_EVENT_WRITE_ZPD:
+CP_EXEC_CS:
+CP_EXEC_CS_INDIRECT:
+CP_FIXED_STRIDE_DRAW_TABLE:
+CP_GLOBAL_TIMESTAMP:
+CP_IM_LOAD:
+CP_IM_LOAD_IMMEDIATE:
+CP_INDIRECT_BUFFER:
+CP_INDIRECT_BUFFER_CHAIN:
+CP_INDIRECT_BUFFER_PFD:
+CP_INTERRUPT:
+CP_INVALIDATE_STATE:
+CP_LOAD_STATE6:
+CP_LOAD_STATE6_FRAG:
+CP_LOAD_STATE6_GEOM:
+CP_LOCAL_TIMESTAMP:
+CP_MEMCPY:
+CP_MEM_TO_MEM:
+CP_MEM_TO_REG:
+CP_MEM_TO_SCRATCH_MEM:
+CP_MEM_WRITE:
+CP_MEM_WRITE_CNTR:
+CP_ME_INIT:
+CP_MODIFY_TIMESTAMP:
+CP_NOP:
+CP_RECORD_PFP_TIMESTAMP:
+CP_REG_RMW:
+CP_REG_TEST:
+CP_REG_TO_MEM:
+CP_REG_TO_MEM_OFFSET_MEM:
+CP_REG_TO_MEM_OFFSET_REG:
+CP_REG_TO_SCRATCH:
+CP_REG_WR_NO_CTXT:
+CP_RESET_CONTEXT_STATE:
+CP_RESOURCE_LIST:
+CP_RUN_OPENCL:
+CP_SCRATCH_TO_REG:
+CP_SET_BIN_DATA5:
+CP_SET_BIN_DATA5_OFFSET:
+CP_SET_CTXSWITCH_IB:
+CP_SET_DRAW_INIT_FLAGS:
+CP_SET_DRAW_STATE:
+CP_SET_MARKER:
+CP_SET_MODE:
+CP_SET_PROTECTED_MODE:
+CP_SET_PSEUDO_REG:
+CP_SET_SECURE_MODE:
+CP_SET_STATE:
+CP_SET_SUBDRAW_SIZE:
+CP_SET_UNK_BIN_DATA:
+CP_SET_VISIBILITY_OVERRIDE:
+CP_SKIP_IB2_ENABLE_GLOBAL:
+CP_SKIP_IB2_ENABLE_LOCAL:
+CP_SMMU_TABLE_UPDATE:
+CP_START_BIN:
+CP_TEST_TWO_MEMS:
+CP_THREAD_CONTROL:
+CP_WAIT_FOR_IDLE:
+CP_WAIT_FOR_ME:
+CP_WAIT_MEM_WRITES:
+CP_WAIT_REG_EQ:
+CP_WAIT_REG_MEM:
+CP_WAIT_TIMESTAMP:
+CP_WHERE_AM_I:
+IN_GMU_INTERRUPT:
+IN_IB_END:
+IN_PREEMPT:
+PKT4:
+UNKN0:
+UNKN1:
+UNKN103:
+UNKN104:
+UNKN105:
+UNKN106:
+UNKN108:
+UNKN109:
+UNKN110:
+UNKN112:
+UNKN118:
+UNKN119:
+UNKN12:
+UNKN121:
+UNKN122:
+UNKN123:
+UNKN124:
+UNKN125:
+UNKN126:
+UNKN13:
+UNKN14:
+UNKN2:
+UNKN3:
+UNKN30:
+UNKN32:
+UNKN48:
+UNKN5:
+UNKN6:
+UNKN7:
+UNKN76:
+UNKN8:
+UNKN84:
+UNKN9:
+UNKN90:
+UNKN96:
+UNKN97:
+waitin
+mov $01, $data
+jumptbl:
+.jumptbl
+[0100beef]
diff --git a/src/freedreno/.gitlab-ci/reference/afuc_test_a7xx.fw b/src/freedreno/.gitlab-ci/reference/afuc_test_a7xx.fw
new file mode 100644
index 0000000000000000000000000000000000000000..7fb479ccdf938d2ed5e31f6a5360268a772776d8
GIT binary patch
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zsMj{q+K_i!IwQCHuop0P%F2Jlw%5GhVV;Q&<MMxqyZsye$T?l%oZNnoZtkZ#sPnuP
z^XMO9_58^K%!LGVAu%(dTl2=u3>?YypIOsB^kBH;;=Y0IKNp}+5`0^_*MF^k8%BR!
La&h0_c#GHx@2e(0

literal 0
HcmV?d00001

diff --git a/src/freedreno/.gitlab-ci/traces/afuc_test_a7xx.asm b/src/freedreno/.gitlab-ci/traces/afuc_test_a7xx.asm
new file mode 100644
index 00000000000..0c95c610bc1
--- /dev/null
+++ b/src/freedreno/.gitlab-ci/traces/afuc_test_a7xx.asm
@@ -0,0 +1,725 @@
+; Copyright (c) 2020 Valve Corporation
+;
+; Permission is hereby granted, free of charge, to any person obtaining a
+; copy of this software and associated documentation files (the "Software"),
+; to deal in the Software without restriction, including without limitation
+; the rights to use, copy, modify, merge, publish, distribute, sublicense,
+; and/or sell copies of the Software, and to permit persons to whom the
+; Software is furnished to do so, subject to the following conditions:
+;
+; The above copyright notice and this permission notice (including the next
+; paragraph) shall be included in all copies or substantial portions of the
+; Software.
+;
+; THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+; FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+; THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+; LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+; OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+; SOFTWARE.
+;
+;
+; This file is the source for a simple mock firmware used to regression test
+; the afuc assembler/disassembler. This is the a7xx variant, for testing new
+; features introduced in a7xx.
+[01000001]
+[#jumptbl]
+loc02:
+; packet table loading:
+mov $01, 0x0830 ; CP_SQE_INSTR_BASE
+mov $02, 0x0002
+cwrite $01, [$00 + @REG_READ_ADDR]
+cwrite $02, [$00 + @REG_READ_DWORDS]
+; move hi/lo of SQE fw addrs to registers:
+mov $01, $regdata
+mov $02, $regdata
+; skip first dword
+add $01, $01, 0x0004
+addhi $02, $02, 0x0000
+mov $03, 0x0001
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $03, [$00 + @MEM_READ_DWORDS]
+; read 2nd dword of fw, and add offset (minus 4 because we skipped first dword)
+; to base address of sqe fw
+rot $04, $memdata, 0x0008
+ushr $04, $04, 0x0006
+sub $04, $04, 0x0004
+add $01, $01, $04
+addhi $02, $02, 0x0000
+
+; load packet table:
+mov $rem, 0x0080
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $02, [$00 + @LOAD_STORE_HI]
+cwrite $rem, [$00 + @MEM_READ_DWORDS]
+cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
+(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
+
+; load BV SQE base address, which should be after the packet table:
+add $01, $01, 0x200
+addhi $02, $02, 0x0
+cwrite $01, [$00 + @BV_INSTR_BASE]
+cwrite $02, [$00 + @BV_INSTR_BASE+1]
+
+; kick off the BV
+cwrite $03, [$00 + @BV_CNTL]
+
+; get BV packet table offset:
+add $01, $01, 0x4
+addhi $02, $02, 0
+
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+1]
+cwrite $03, [$00 + @MEM_READ_DWORDS]
+
+rot $04, $memdata, 8
+ushr $04, $04, 6
+sub $04, $04, 4
+add $01, $01, $04
+addhi $02, $02, 0x0
+
+; load LPAC base address, which is after the BV packet table
+add $01, $01, 0x200
+addhi $02, $02, 0x0
+
+cwrite $01, [$00 + @LPAC_INSTR_BASE]
+cwrite $02, [$00 + @LPAC_INSTR_BASE+1]
+
+; kick off the LPAC
+cwrite $03, [$00 + @LPAC_CNTL]
+
+mov $02, 0x883
+mov $03, 0xbeef
+mov $04, 0xdead << 16
+or $03, $03, $04
+cwrite $02, [$00 + @REG_WRITE_ADDR]
+cwrite $03, [$00 + @REG_WRITE]
+waitin
+mov $01, $data
+
+CP_ME_INIT:
+; test label-as-immediate feature
+mov $02, #loc02 ; should be 0x0002
+waitin
+mov $01, $data
+
+CP_MEM_WRITE:
+; test $addr + (rep) + (xmovN) with ALU
+mov $addr, 0xa0 << 24
+mov $02, 4
+(xmov1)add $data, $02, $data
+mov $addr, 0xa204 << 16
+(rep)(xmov3)mov $data, $data
+waitin
+mov $01, $data
+
+CP_SCRATCH_WRITE:
+; test (rep) + preincrement + non-zero offset with cwrite
+mov $02, 0xff
+(rep)cwrite $data, [$02 + 0x001]!
+waitin
+mov $01, $data
+
+CP_SET_DRAW_STATE:
+; test (sds)
+(rep)(sds2) cwrite $data, [$00 + @DRAW_STATE_SET_HDR]
+waitin
+mov $01, $data
+
+CP_SET_BIN_DATA5:
+; test SQE registers
+sread $02, [$00 + %SP]
+swrite $02, [$00 + %SP]
+mov $02, 7
+(rep)swrite $data, [$02 + 1]!
+waitin
+mov $01, $data
+
+CP_SET_SECURE_MODE:
+; test setsecure
+mov $02, $data
+setsecure $02, #setsecure_success
+err:
+jump #err
+nop
+setsecure_success:
+waitin
+mov $01, $data
+
+euclid:
+; Euclid's algorithm in afuc: https://en.wikipedia.org/wiki/Euclidean_algorithm
+; Since afuc doesn't do modulo, we implement the subtraction-based version.
+;
+; Demonstrates/tests comparisons and conditional branches. This also
+; demonstrates the common trick of branching in a delay slot. Note that if a
+; branch is taken and its delay slot includes another branch, the second
+; branch cannot also be taken, which is why the last branch in the sequence
+; cannot be unconditional.
+;
+; Inputs are in $02 and $03, and output is in $02.
+cmp $04, $02, $03
+breq $04, b0, #euclid_exit
+brne $04, b1, #euclid_gt
+breq $04, b2, #euclid
+sub $03, $03, $02
+euclid_gt:
+jump #euclid
+sub $02, $02, $03
+euclid_exit:
+ret
+nop
+
+CP_REG_RMW:
+; Test various ALU instructions, and read/write $regdata
+cwrite $data, [$00 + @REG_READ_ADDR]
+add $02, $regdata, 0x42
+addhi $03, $00, $regdata
+sub $02, $02, $regdata
+call #euclid
+subhi $03, $03, $regdata
+and $02, $02, $regdata
+or $02, $02, 0x1
+xor $02, $02, 0x1
+not $02, $02
+shl $02, $02, $regdata
+ushr $02, $02, $regdata
+ishr $02, $02, $regdata
+rot $02, $02, $regdata
+min $02, $02, $regdata
+max $02, $02, $regdata
+mul8 $02, $02, $regdata
+bic $02, $02, $regdata
+msb $02, $02
+bfi $02, $03, b1, b2
+setbit $02, $02, b3
+clrbit $02, $02, b4
+setbit $02, $02, $03
+ubfx $03, $02, b5, b6
+mov $usraddr, $data
+mov $data, $02
+(peek)mov $00, $data
+waitin
+mov $01, $data
+
+CP_MEMCPY:
+; implement CP_MEMCPY using load/store instructions
+mov $02, $data
+mov $03, $data
+mov $04, $data
+mov $05, $data
+mov $06, $data
+cpy_header:
+breq $06, 0, #cpy_exit
+cwrite $03, [$00 + @LOAD_STORE_HI]
+load $07, [$02 + 0x004]!
+cwrite $05, [$00 + @LOAD_STORE_HI]
+jump #cpy_header
+store $07, [$04 + 0x004]!
+cpy_exit:
+waitin
+mov $01, $data
+
+CP_MEM_TO_MEM:
+; implement CP_MEMCPY using mem read control regs
+; tests @FOO+0x1 for 64-bit control regs, and reading/writing $rem
+cwrite $data, [$00 + @MEM_READ_ADDR]
+cwrite $data, [$00 + @MEM_READ_ADDR+1]
+mov $02, $data
+cwrite $data, [$00 + @LOAD_STORE_HI]
+mov $rem, $data
+cwrite $rem, [$00 + @MEM_READ_DWORDS]
+(rep)store $memdata, [$02 + 0x004]!
+waitin
+mov $01, $data
+
+IN_PREEMPT:
+; test preemptleave + iret + conditional branch w/ immed
+cread $02, [$00 + 0x101]
+brne $02, 0x0001, #exit_iret
+nop
+preemptleave #err
+nop
+nop
+nop
+waitin
+mov $01, $data
+exit_iret:
+iret
+nop
+
+UNKN0:
+UNKN1:
+UNKN2:
+UNKN3:
+PKT4:
+UNKN5:
+UNKN6:
+UNKN7:
+UNKN8:
+UNKN9:
+UNKN10:
+UNKN11:
+UNKN12:
+UNKN13:
+UNKN14:
+CP_NOP:
+CP_RECORD_PFP_TIMESTAMP:
+CP_WAIT_MEM_WRITES:
+CP_WAIT_FOR_ME:
+CP_WAIT_MEM_GTE:
+UNKN21:
+UNKN22:
+UNKN23:
+UNKN24:
+CP_DRAW_PRED_ENABLE_GLOBAL:
+CP_DRAW_PRED_ENABLE_LOCAL:
+UNKN27:
+CP_PREEMPT_ENABLE:
+CP_SKIP_IB2_ENABLE_GLOBAL:
+CP_PREEMPT_TOKEN:
+UNKN31:
+UNKN32:
+CP_DRAW_INDX:
+CP_SKIP_IB2_ENABLE_LOCAL:
+CP_DRAW_AUTO:
+CP_SET_STATE:
+CP_WAIT_FOR_IDLE:
+CP_IM_LOAD:
+CP_DRAW_INDIRECT:
+CP_DRAW_INDX_INDIRECT:
+CP_DRAW_INDIRECT_MULTI:
+CP_IM_LOAD_IMMEDIATE:
+CP_BLIT:
+CP_SET_CONSTANT:
+CP_SET_BIN_DATA5_OFFSET:
+UNKN48:
+CP_RUN_OPENCL:
+CP_LOAD_STATE6_GEOM:
+CP_EXEC_CS:
+CP_LOAD_STATE6_FRAG:
+CP_SET_SUBDRAW_SIZE:
+CP_LOAD_STATE6:
+CP_INDIRECT_BUFFER_PFD:
+CP_DRAW_INDX_OFFSET:
+CP_REG_TEST:
+CP_COND_INDIRECT_BUFFER_PFE:
+CP_INVALIDATE_STATE:
+CP_WAIT_REG_MEM:
+CP_REG_TO_MEM:
+CP_INDIRECT_BUFFER:
+CP_INTERRUPT:
+CP_EXEC_CS_INDIRECT:
+CP_MEM_TO_REG:
+CP_COND_EXEC:
+CP_COND_WRITE5:
+CP_EVENT_WRITE:
+CP_COND_REG_EXEC:
+UNKN73:
+CP_REG_TO_SCRATCH:
+CP_SET_DRAW_INIT_FLAGS:
+CP_SCRATCH_TO_REG:
+CP_DRAW_PRED_SET:
+CP_MEM_WRITE_CNTR:
+CP_START_BIN:
+CP_END_BIN:
+CP_WAIT_REG_EQ:
+CP_SMMU_TABLE_UPDATE:
+UNKN84:
+CP_SET_CTXSWITCH_IB:
+CP_SET_PSEUDO_REG:
+CP_INDIRECT_BUFFER_CHAIN:
+CP_EVENT_WRITE_SHD:
+CP_EVENT_WRITE_CFL:
+UNKN90:
+CP_EVENT_WRITE_ZPD:
+CP_CONTEXT_REG_BUNCH:
+CP_WAIT_IB_PFD_COMPLETE:
+CP_CONTEXT_UPDATE:
+CP_SET_PROTECTED_MODE:
+UNKN96:
+UNKN97:
+UNKN98:
+CP_SET_MODE:
+CP_SET_VISIBILITY_OVERRIDE:
+CP_SET_MARKER:
+UNKN103:
+UNKN104:
+UNKN105:
+UNKN106:
+UNKN107:
+UNKN108:
+CP_REG_WRITE:
+UNKN110:
+CP_BOOTSTRAP_UCODE:
+CP_WAIT_TWO_REGS:
+CP_TEST_TWO_MEMS:
+CP_REG_TO_MEM_OFFSET_REG:
+CP_REG_TO_MEM_OFFSET_MEM:
+UNKN118:
+UNKN119:
+CP_REG_WR_NO_CTXT:
+UNKN121:
+UNKN122:
+UNKN123:
+UNKN124:
+UNKN125:
+UNKN126:
+UNKN127:
+        waitin
+        mov $01, $data
+
+.align 32
+jumptbl:
+.jumptbl
+
+.section BV
+; BV microcode
+
+[01000001]
+[#jumptbl]
+
+; read BV fw addr
+cread $01, [$00 + @BV_INSTR_BASE]
+cread $02, [$00 + @BV_INSTR_BASE+1]
+
+; skip first dword
+add $01, $01, 0x0004
+addhi $02, $02, 0x0000
+mov $03, 0x0001
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $03, [$00 + @MEM_READ_DWORDS]
+; read 2nd dword of fw, and add offset (minus 4 because we skipped first dword)
+; to base address of sqe fw
+rot $04, $memdata, 0x0008
+ushr $04, $04, 0x0006
+sub $04, $04, 0x0004
+add $01, $01, $04
+addhi $02, $02, 0x0000
+
+; load packet table:
+mov $rem, 0x0080
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $02, [$00 + @LOAD_STORE_HI]
+cwrite $rem, [$00 + @MEM_READ_DWORDS]
+cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
+(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
+
+; load LPAC SQE base address, which should be after the packet table:
+add $01, $01, 0x200
+addhi $02, $02, 0x0
+cwrite $01, [$00 + @LPAC_INSTR_BASE]
+cwrite $02, [$00 + @LPAC_INSTR_BASE+1]
+
+waitin
+mov $01, $data
+
+CP_ME_INIT:
+CP_MEM_WRITE:
+CP_SCRATCH_WRITE:
+CP_SET_DRAW_STATE:
+CP_SET_BIN_DATA5:
+CP_SET_SECURE_MODE:
+CP_REG_RMW:
+CP_MEMCPY:
+CP_MEM_TO_MEM:
+IN_PREEMPT:
+UNKN0:
+UNKN1:
+UNKN2:
+UNKN3:
+PKT4:
+UNKN5:
+UNKN6:
+UNKN7:
+UNKN8:
+UNKN9:
+UNKN10:
+UNKN11:
+UNKN12:
+UNKN13:
+UNKN14:
+CP_NOP:
+CP_RECORD_PFP_TIMESTAMP:
+CP_WAIT_MEM_WRITES:
+CP_WAIT_FOR_ME:
+CP_WAIT_MEM_GTE:
+UNKN21:
+UNKN22:
+UNKN23:
+UNKN24:
+CP_DRAW_PRED_ENABLE_GLOBAL:
+CP_DRAW_PRED_ENABLE_LOCAL:
+UNKN27:
+CP_PREEMPT_ENABLE:
+CP_SKIP_IB2_ENABLE_GLOBAL:
+CP_PREEMPT_TOKEN:
+UNKN31:
+UNKN32:
+CP_DRAW_INDX:
+CP_SKIP_IB2_ENABLE_LOCAL:
+CP_DRAW_AUTO:
+CP_SET_STATE:
+CP_WAIT_FOR_IDLE:
+CP_IM_LOAD:
+CP_DRAW_INDIRECT:
+CP_DRAW_INDX_INDIRECT:
+CP_DRAW_INDIRECT_MULTI:
+CP_IM_LOAD_IMMEDIATE:
+CP_BLIT:
+CP_SET_CONSTANT:
+CP_SET_BIN_DATA5_OFFSET:
+UNKN48:
+CP_RUN_OPENCL:
+CP_LOAD_STATE6_GEOM:
+CP_EXEC_CS:
+CP_LOAD_STATE6_FRAG:
+CP_SET_SUBDRAW_SIZE:
+CP_LOAD_STATE6:
+CP_INDIRECT_BUFFER_PFD:
+CP_DRAW_INDX_OFFSET:
+CP_REG_TEST:
+CP_COND_INDIRECT_BUFFER_PFE:
+CP_INVALIDATE_STATE:
+CP_WAIT_REG_MEM:
+CP_REG_TO_MEM:
+CP_INDIRECT_BUFFER:
+CP_INTERRUPT:
+CP_EXEC_CS_INDIRECT:
+CP_MEM_TO_REG:
+CP_COND_EXEC:
+CP_COND_WRITE5:
+CP_EVENT_WRITE:
+CP_COND_REG_EXEC:
+UNKN73:
+CP_REG_TO_SCRATCH:
+CP_SET_DRAW_INIT_FLAGS:
+CP_SCRATCH_TO_REG:
+CP_DRAW_PRED_SET:
+CP_MEM_WRITE_CNTR:
+CP_START_BIN:
+CP_END_BIN:
+CP_WAIT_REG_EQ:
+CP_SMMU_TABLE_UPDATE:
+UNKN84:
+CP_SET_CTXSWITCH_IB:
+CP_SET_PSEUDO_REG:
+CP_INDIRECT_BUFFER_CHAIN:
+CP_EVENT_WRITE_SHD:
+CP_EVENT_WRITE_CFL:
+UNKN90:
+CP_EVENT_WRITE_ZPD:
+CP_CONTEXT_REG_BUNCH:
+CP_WAIT_IB_PFD_COMPLETE:
+CP_CONTEXT_UPDATE:
+CP_SET_PROTECTED_MODE:
+UNKN96:
+UNKN97:
+UNKN98:
+CP_SET_MODE:
+CP_SET_VISIBILITY_OVERRIDE:
+CP_SET_MARKER:
+UNKN103:
+UNKN104:
+UNKN105:
+UNKN106:
+UNKN107:
+UNKN108:
+CP_REG_WRITE:
+UNKN110:
+CP_BOOTSTRAP_UCODE:
+CP_WAIT_TWO_REGS:
+CP_TEST_TWO_MEMS:
+CP_REG_TO_MEM_OFFSET_REG:
+CP_REG_TO_MEM_OFFSET_MEM:
+UNKN118:
+UNKN119:
+CP_REG_WR_NO_CTXT:
+UNKN121:
+UNKN122:
+UNKN123:
+UNKN124:
+UNKN125:
+UNKN126:
+UNKN127:
+waitin
+mov $01, $data
+
+.align 32
+jumptbl:
+.jumptbl
+
+.section LPAC
+; LPAC microcode
+[01000001]
+[#jumptbl]
+
+; read LPAC fw addr
+cread $01, [$00 + @LPAC_INSTR_BASE]
+cread $02, [$00 + @LPAC_INSTR_BASE+1]
+
+; skip first dword
+add $01, $01, 0x0004
+addhi $02, $02, 0x0000
+mov $03, 0x0001
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $03, [$00 + @MEM_READ_DWORDS]
+; read 2nd dword of fw, and add offset (minus 4 because we skipped first dword)
+; to base address of sqe fw
+rot $04, $memdata, 0x0008
+ushr $04, $04, 0x0006
+sub $04, $04, 0x0004
+add $01, $01, $04
+addhi $02, $02, 0x0000
+
+; load packet table:
+mov $rem, 0x0080
+cwrite $01, [$00 + @MEM_READ_ADDR]
+cwrite $02, [$00 + @MEM_READ_ADDR+0x1]
+cwrite $02, [$00 + @LOAD_STORE_HI]
+cwrite $rem, [$00 + @MEM_READ_DWORDS]
+cwrite $00, [$00 + @PACKET_TABLE_WRITE_ADDR]
+(rep)cwrite $memdata, [$00 + @PACKET_TABLE_WRITE]
+
+CP_ME_INIT:
+CP_MEM_WRITE:
+CP_SCRATCH_WRITE:
+CP_SET_DRAW_STATE:
+CP_SET_BIN_DATA5:
+CP_SET_SECURE_MODE:
+CP_REG_RMW:
+CP_MEMCPY:
+CP_MEM_TO_MEM:
+IN_PREEMPT:
+UNKN0:
+UNKN1:
+UNKN2:
+UNKN3:
+PKT4:
+UNKN5:
+UNKN6:
+UNKN7:
+UNKN8:
+UNKN9:
+UNKN10:
+UNKN11:
+UNKN12:
+UNKN13:
+UNKN14:
+CP_NOP:
+CP_RECORD_PFP_TIMESTAMP:
+CP_WAIT_MEM_WRITES:
+CP_WAIT_FOR_ME:
+CP_WAIT_MEM_GTE:
+UNKN21:
+UNKN22:
+UNKN23:
+UNKN24:
+CP_DRAW_PRED_ENABLE_GLOBAL:
+CP_DRAW_PRED_ENABLE_LOCAL:
+UNKN27:
+CP_PREEMPT_ENABLE:
+CP_SKIP_IB2_ENABLE_GLOBAL:
+CP_PREEMPT_TOKEN:
+UNKN31:
+UNKN32:
+CP_DRAW_INDX:
+CP_SKIP_IB2_ENABLE_LOCAL:
+CP_DRAW_AUTO:
+CP_SET_STATE:
+CP_WAIT_FOR_IDLE:
+CP_IM_LOAD:
+CP_DRAW_INDIRECT:
+CP_DRAW_INDX_INDIRECT:
+CP_DRAW_INDIRECT_MULTI:
+CP_IM_LOAD_IMMEDIATE:
+CP_BLIT:
+CP_SET_CONSTANT:
+CP_SET_BIN_DATA5_OFFSET:
+UNKN48:
+CP_RUN_OPENCL:
+CP_LOAD_STATE6_GEOM:
+CP_EXEC_CS:
+CP_LOAD_STATE6_FRAG:
+CP_SET_SUBDRAW_SIZE:
+CP_LOAD_STATE6:
+CP_INDIRECT_BUFFER_PFD:
+CP_DRAW_INDX_OFFSET:
+CP_REG_TEST:
+CP_COND_INDIRECT_BUFFER_PFE:
+CP_INVALIDATE_STATE:
+CP_WAIT_REG_MEM:
+CP_REG_TO_MEM:
+CP_INDIRECT_BUFFER:
+CP_INTERRUPT:
+CP_EXEC_CS_INDIRECT:
+CP_MEM_TO_REG:
+CP_COND_EXEC:
+CP_COND_WRITE5:
+CP_EVENT_WRITE:
+CP_COND_REG_EXEC:
+UNKN73:
+CP_REG_TO_SCRATCH:
+CP_SET_DRAW_INIT_FLAGS:
+CP_SCRATCH_TO_REG:
+CP_DRAW_PRED_SET:
+CP_MEM_WRITE_CNTR:
+CP_START_BIN:
+CP_END_BIN:
+CP_WAIT_REG_EQ:
+CP_SMMU_TABLE_UPDATE:
+UNKN84:
+CP_SET_CTXSWITCH_IB:
+CP_SET_PSEUDO_REG:
+CP_INDIRECT_BUFFER_CHAIN:
+CP_EVENT_WRITE_SHD:
+CP_EVENT_WRITE_CFL:
+UNKN90:
+CP_EVENT_WRITE_ZPD:
+CP_CONTEXT_REG_BUNCH:
+CP_WAIT_IB_PFD_COMPLETE:
+CP_CONTEXT_UPDATE:
+CP_SET_PROTECTED_MODE:
+UNKN96:
+UNKN97:
+UNKN98:
+CP_SET_MODE:
+CP_SET_VISIBILITY_OVERRIDE:
+CP_SET_MARKER:
+UNKN103:
+UNKN104:
+UNKN105:
+UNKN106:
+UNKN107:
+UNKN108:
+CP_REG_WRITE:
+UNKN110:
+CP_BOOTSTRAP_UCODE:
+CP_WAIT_TWO_REGS:
+CP_TEST_TWO_MEMS:
+CP_REG_TO_MEM_OFFSET_REG:
+CP_REG_TO_MEM_OFFSET_MEM:
+UNKN118:
+UNKN119:
+CP_REG_WR_NO_CTXT:
+UNKN121:
+UNKN122:
+UNKN123:
+UNKN124:
+UNKN125:
+UNKN126:
+UNKN127:
+waitin
+mov $01, $data
+
+.align 32
+jumptbl:
+.jumptbl
+
+; test junk data after jump table
+[0100beef]
diff --git a/src/freedreno/afuc/meson.build b/src/freedreno/afuc/meson.build
index a226d4240ad..b8e567164b2 100644
--- a/src/freedreno/afuc/meson.build
+++ b/src/freedreno/afuc/meson.build
@@ -74,12 +74,22 @@ if with_tests
     output: 'afuc_test.fw',
     command: [asm, '-g', '6', files('../.gitlab-ci/traces/afuc_test.asm'), '@OUTPUT@'],
   )
+  asm_fw_a7xx = custom_target('afuc_test_a7xx.fw',
+    output: 'afuc_test_a7xx.fw',
+    command: [asm, '-g', '7', files('../.gitlab-ci/traces/afuc_test_a7xx.asm'), '@OUTPUT@'],
+  )
   test('afuc-asm',
     diff,
     args: ['-u', files('../.gitlab-ci/reference/afuc_test.fw'), asm_fw],
     suite: 'freedreno',
     workdir: dir_source_root
   )
+  test('afuc-asm-a7xx',
+    diff,
+    args: ['-u', files('../.gitlab-ci/reference/afuc_test_a7xx.fw'), asm_fw_a7xx],
+    suite: 'freedreno',
+    workdir: dir_source_root
+  )
 endif
 
 afuc_isa = custom_target(
@@ -128,11 +138,22 @@ if cc.sizeof('size_t') > 4
       command: [disasm, '-u', files('../.gitlab-ci/reference/afuc_test.fw'), '-g', '630'],
       capture: true
     )
+    disasm_fw_a7xx = custom_target('afuc_test_a7xx.asm',
+      output: 'afuc_test_a7xx.asm',
+      command: [disasm, '-u', files('../.gitlab-ci/reference/afuc_test_a7xx.fw'), '-g', '730'],
+      capture: true
+    )
     test('afuc-disasm',
       diff,
       args: ['-u', files('../.gitlab-ci/reference/afuc_test.asm'), disasm_fw],
       suite: 'freedreno',
       workdir: dir_source_root
     )
+    test('afuc-disasm-a7xx',
+      diff,
+      args: ['-u', files('../.gitlab-ci/reference/afuc_test_a7xx.asm'), disasm_fw_a7xx],
+      suite: 'freedreno',
+      workdir: dir_source_root
+    )
   endif
 endif