From e76a26579a6283c32a3b15e34e41c5ed4d44d2d6 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 1 Oct 2024 17:53:03 +0200 Subject: [PATCH] radv/amdgpu: add assertions to check the IB size This can be triggered with DGC if the maximum number of sequences count is too high. Luckily, vkd3d-proton doesn't do that, but it should be fixed for EXT DGC. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c index 5cdc5b91595..e0880d18414 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c @@ -481,6 +481,7 @@ radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs) radeon_emit_unchecked(&cs->base, nop_packet); radeon_emit_unchecked(&cs->base, nop_packet); + assert(cs->base.cdw <= ~C_3F2_IB_SIZE); *cs->ib_size_ptr |= cs->base.cdw; } else { radv_amdgpu_winsys_cs_pad(_cs, 0); @@ -806,6 +807,8 @@ radv_amdgpu_cs_execute_ib(struct radeon_cmdbuf *_cs, struct radeon_winsys_bo *bo assert(ib_va && ib_va % cs->ws->info.ip[cs->hw_ip].ib_alignment == 0); if (cs->hw_ip == AMD_IP_GFX && cs->use_ib) { + assert(cdw <= ~C_3F2_IB_SIZE); + radeon_emit(&cs->base, PKT3(PKT3_INDIRECT_BUFFER, 2, predicate)); radeon_emit(&cs->base, ib_va); radeon_emit(&cs->base, ib_va >> 32);