From e762061127f3be73a224529f42f37b7276db9e03 Mon Sep 17 00:00:00 2001
From: Ilia Mirkin <imirkin@alum.mit.edu>
Date: Tue, 9 Mar 2021 23:59:31 -0500
Subject: [PATCH] nv50/ir: optimize shift of 0 bits

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <dev@pmoreau.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10164>
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 792874577a2..8a167d70abf 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1461,6 +1461,12 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
    {
       if (s != 1 || i->src(0).mod != Modifier(0))
          break;
+
+      if (imm0.reg.data.u32 == 0) {
+         i->op = OP_MOV;
+         i->setSrc(1, NULL);
+         break;
+      }
       // try to concatenate shifts
       Instruction *si = i->getSrc(0)->getInsn();
       if (!si)