Mesa 17.2.6 Release Notes / November 25, 2017
+ ++Mesa 17.2.6 is a bug fix release which fixes bugs found since the 17.2.5 release. +
++Mesa 17.2.6 implements the OpenGL 4.5 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.5. OpenGL +4.5 is only available if requested at context creation +because compatibility contexts are not supported. +
+ + +SHA256 checksums
++TBD ++ + +
New features
+None
+ + +Bug fixes
+-
+
+
- Bug 100438 - glsl/ir.cpp:1376: ir_dereference_variable::ir_dereference_variable(ir_variable*): Assertion `var != NULL' failed. + +
- Bug 102177 - [SKL] ES31-CTS.core.sepshaderobjs.StateInteraction fails sporadically + +
- Bug 103115 - [BSW BXT GLK] dEQP-VK.spirv_assembly.instruction.compute.sconvert.int32_to_int64 + +
- Bug 103519 - wayland egl apps crash on start with mesa 17.2 + +
- Bug 103529 - [GM45] GPU hang with mpv fullscreen (bisected) + +
- Bug 103626 - [SNB] ES3-CTS.functional.shaders.precision + +
- Bug 103628 - [BXT, GLK, BSW] KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks + +
- Bug 103787 - [BDW,BSW] gpu hang on spec.arb_pipeline_statistics_query.arb_pipeline_statistics_query-comp + +
Changes
+Adam Jackson (2):
+-
+
- glx/drisw: Fix glXMakeCurrent(dpy, None, ctx) +
- glx/dri3: Fix passing renderType into glXCreateContext +
Alex Smith (2):
+-
+
- spirv: Use correct type for sampled images +
- nir/spirv: tg4 requires a sampler +
Andres Gomez (14):
+-
+
- docs: add sha256 checksums for 17.2.5 +
- cherry-ignore: intel/fs: Use a pure vertical stride for large register strides +
- cherry-ignore: intel/nir: Use the correct indirect lowering masks in link_shaders +
- cherry-ignore: intel/fs: Use the original destination region for int MUL lowering +
- cherry-ignore: intel/fs: refactors +
- cherry-ignore: r600/shader: reserve first register of vertex shader. +
- cherry-ignore: anv/cmd_buffer: Advance the address when initializing clear colors +
- cherry-ignore: anv/cmd_buffer: Take bo_offset into account in fast clear state addresses +
- cherry-ignore: i965: Mark BOs as external when we export their handle +
- cherry-ignore: added 17.3 nominations. +
- cherry-ignore: glsl: Fix typo fragement -> fragment +
- cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions +
- cherry-ignore: Revert "intel/fs: Use a pure vertical stride for large register strides" +
- Update version to 17.2.6 +
Anuj Phogat (2):
+-
+
- i965: Program DWord Length in MI_FLUSH_DW +
- i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW +
Bas Nieuwenhuizen (2):
+-
+
- radv: Free syncobj with multiple imports. +
- radv: Free temporary syncobj after waiting on it. +
Dave Airlie (1):
+-
+
- r600: fix isoline tess factor component swapping. +
Derek Foreman (1):
+-
+
- egl/wayland: Add a fallback when fourcc query isn't supported +
Dylan Baker (1):
+-
+
- autotools: Set C++ visibility flags on Intel +
Emil Velikov (3):
+-
+
- targets/opencl: don't hardcode the icd file install to /etc/... +
- configure.ac: loosen --enable-glvnd check to honour egl +
- configure.ac: require xcb* for the omx/va/... when using x11 platform +
George Barrett (1):
+-
+
- glsl: Catch subscripted calls to undeclared subroutines +
Jason Ekstrand (9):
+-
+
- intel/fs: Use ANY/ALL32 predicates in SIMD32 +
- intel/fs: Use an explicit D type for vote any/all/eq intrinsics +
- intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all +
- intel/eu/reg: Add a subscript() helper +
- intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core +
- intel/fs: Fix integer multiplication lowering for src/dst hazards +
- intel/fs: Mark 64-bit values as being contiguous +
- intel/fs: Rework zero-length URB write handling +
- i965: Add stencil buffers to cache set regardless of stencil texturing +
Kenneth Graunke (5):
+-
+
- i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE +
- i965: Make L3 configuration atom listen for TCS/TES program updates. +
- intel/tools: Fix detection of enabled shader stages. +
- i965: Implement another VF cache invalidate workaround on Gen8+. +
- i965: Upload invariant state once at the start of the batch on Gen4-5. +
Matt Turner (2):
+-
+
- i965/fs: Fix extract_i8/u8 to a 64-bit destination +
- i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK +
Neil Roberts (1):
+-
+
- glsl: Transform fb buffers are only active if a variable uses them +
Nicolai Hähnle (1):
+-
+
- ddebug: fix use-after-free of streamout targets +
Tim Rowley (2):
+-
+
- swr/rast: Use gather instruction for i32gather_ps on simd16/avx512 +
- swr/rast: Faster emulated simd16 permute +
Timothy Arceri (3):
+-
+
- glsl: drop cache_fallback +
- glsl: use the correct parent when allocating program data members +
- mesa: rework how we free gl_shader_program_data +