From e6a5c342da9fe4efaf5d1df74c6fdf881245037c Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Tue, 1 Oct 2024 07:40:54 +0200 Subject: [PATCH] nir/lower_int64: add nir_intrinsic_read_invocation_cond_ir3 Can simply be split into 32b ops. Signed-off-by: Job Noorman Reviewed-by: Connor Abbott Part-of: --- src/compiler/nir/nir_lower_int64.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/nir/nir_lower_int64.c b/src/compiler/nir/nir_lower_int64.c index 979249a9690..6ff522a3fd5 100644 --- a/src/compiler/nir/nir_lower_int64.c +++ b/src/compiler/nir/nir_lower_int64.c @@ -1256,6 +1256,7 @@ should_lower_int64_intrinsic(const nir_intrinsic_instr *intrin, switch (intrin->intrinsic) { case nir_intrinsic_read_invocation: case nir_intrinsic_read_first_invocation: + case nir_intrinsic_read_invocation_cond_ir3: case nir_intrinsic_shuffle: case nir_intrinsic_shuffle_xor: case nir_intrinsic_shuffle_up: @@ -1300,6 +1301,7 @@ lower_int64_intrinsic(nir_builder *b, nir_intrinsic_instr *intrin) switch (intrin->intrinsic) { case nir_intrinsic_read_invocation: case nir_intrinsic_read_first_invocation: + case nir_intrinsic_read_invocation_cond_ir3: case nir_intrinsic_shuffle: case nir_intrinsic_shuffle_xor: case nir_intrinsic_shuffle_up: