From e68f81eaf636195b0eb62d4cb05b25a70599a820 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Date: Mon, 23 Jun 2025 12:02:14 -0700 Subject: [PATCH] anv: Read the correct register for aux table invalidation when in GPGPU mode in render engine MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For 3D or GPGPU modes the same render engine should be used, CCS register should only be used when using compute engine. Fixes: 46f5359238ed ("anv: Invalidate aux map for copy/video engine") Reviewed-by: Ivan Briano Reviewed-by: Lionel Landwerlin Signed-off-by: José Roberto de Souza Part-of: --- src/intel/vulkan/genX_cmd_buffer.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index c72dd2202ed..9c78ec21413 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1846,10 +1846,7 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch, genx_batch_emit_pipe_control_write(batch, device->info, current_pipeline, sync_op, addr, 0, bits); - enum intel_engine_class engine_class = - current_pipeline == GPGPU ? INTEL_ENGINE_CLASS_COMPUTE : - INTEL_ENGINE_CLASS_RENDER; - genX(invalidate_aux_map)(batch, device, engine_class, bits); + genX(invalidate_aux_map)(batch, device, batch->engine_class, bits); bits &= ~ANV_PIPE_INVALIDATE_BITS; }