From e5c5a983f72eb6580446011334a5e6324eff0fab Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Tue, 20 Feb 2024 21:12:17 -0800 Subject: [PATCH] intel/brw: Move functions from backend_instruction into fs_inst Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_fs.cpp | 68 +++++++++++++++++-- src/intel/compiler/brw_fs.h | 5 +- src/intel/compiler/brw_ir.h | 34 ---------- src/intel/compiler/brw_ir_fs.h | 35 +++++++++- src/intel/compiler/brw_shader.cpp | 104 +++++------------------------- 5 files changed, 113 insertions(+), 133 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 40d397652f9..87d9554a492 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -448,17 +448,75 @@ fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const return false; } - if (!backend_instruction::can_do_source_mods()) + switch (opcode) { + case BRW_OPCODE_ADDC: + case BRW_OPCODE_BFE: + case BRW_OPCODE_BFI1: + case BRW_OPCODE_BFI2: + case BRW_OPCODE_BFREV: + case BRW_OPCODE_CBIT: + case BRW_OPCODE_FBH: + case BRW_OPCODE_FBL: + case BRW_OPCODE_ROL: + case BRW_OPCODE_ROR: + case BRW_OPCODE_SUBB: + case BRW_OPCODE_DP4A: + case BRW_OPCODE_DPAS: + case SHADER_OPCODE_BROADCAST: + case SHADER_OPCODE_CLUSTER_BROADCAST: + case SHADER_OPCODE_MOV_INDIRECT: + case SHADER_OPCODE_SHUFFLE: + case SHADER_OPCODE_INT_QUOTIENT: + case SHADER_OPCODE_INT_REMAINDER: return false; - - return true; + default: + return true; + } } bool -fs_inst::can_do_cmod() +fs_inst::can_do_cmod() const { - if (!backend_instruction::can_do_cmod()) + switch (opcode) { + case BRW_OPCODE_ADD: + case BRW_OPCODE_ADD3: + case BRW_OPCODE_ADDC: + case BRW_OPCODE_AND: + case BRW_OPCODE_ASR: + case BRW_OPCODE_AVG: + case BRW_OPCODE_CMP: + case BRW_OPCODE_CMPN: + case BRW_OPCODE_DP2: + case BRW_OPCODE_DP3: + case BRW_OPCODE_DP4: + case BRW_OPCODE_DPH: + case BRW_OPCODE_FRC: + case BRW_OPCODE_LINE: + case BRW_OPCODE_LRP: + case BRW_OPCODE_LZD: + case BRW_OPCODE_MAC: + case BRW_OPCODE_MACH: + case BRW_OPCODE_MAD: + case BRW_OPCODE_MOV: + case BRW_OPCODE_MUL: + case BRW_OPCODE_NOT: + case BRW_OPCODE_OR: + case BRW_OPCODE_PLN: + case BRW_OPCODE_RNDD: + case BRW_OPCODE_RNDE: + case BRW_OPCODE_RNDU: + case BRW_OPCODE_RNDZ: + case BRW_OPCODE_SAD2: + case BRW_OPCODE_SADA2: + case BRW_OPCODE_SHL: + case BRW_OPCODE_SHR: + case BRW_OPCODE_SUBB: + case BRW_OPCODE_XOR: + case FS_OPCODE_LINTERP: + break; + default: return false; + } /* The accumulator result appears to get used for the conditional modifier * generation. When negating a UD value, there is a 33rd bit generated for diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index e9a87cb2772..06acf17a5c7 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -330,10 +330,7 @@ public: /** ralloc context for temporary data used during compile */ void *mem_ctx; - /** - * List of either fs_inst or vec4_instruction (inheriting from - * backend_instruction) - */ + /** List of fs_inst. */ exec_list instructions; cfg_t *cfg; diff --git a/src/intel/compiler/brw_ir.h b/src/intel/compiler/brw_ir.h index 8a78861b62c..beef9a473e0 100644 --- a/src/intel/compiler/brw_ir.h +++ b/src/intel/compiler/brw_ir.h @@ -95,40 +95,6 @@ struct backend_reg : private brw_reg struct bblock_t; struct backend_instruction : public exec_node { - bool is_3src(const struct brw_compiler *compiler) const; - bool is_math() const; - bool is_control_flow_begin() const; - bool is_control_flow_end() const; - bool is_control_flow() const; - bool is_commutative() const; - bool can_do_source_mods() const; - bool can_do_saturate() const; - bool can_do_cmod() const; - bool reads_accumulator_implicitly() const; - bool writes_accumulator_implicitly(const struct intel_device_info *devinfo) const; - - /** - * Instructions that use indirect addressing have additional register - * regioning restrictions. - */ - bool uses_indirect_addressing() const; - - void remove(bblock_t *block, bool defer_later_block_ip_updates = false); - void insert_after(bblock_t *block, backend_instruction *inst); - void insert_before(bblock_t *block, backend_instruction *inst); - - /** - * True if the instruction has side effects other than writing to - * its destination registers. You are expected not to reorder or - * optimize these out unless you know what you are doing. - */ - bool has_side_effects() const; - - /** - * True if the instruction might be affected by side effects of other - * instructions. - */ - bool is_volatile() const; #else struct backend_instruction { struct exec_node link; diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h index 82ca907c625..b5af50b28d7 100644 --- a/src/intel/compiler/brw_ir_fs.h +++ b/src/intel/compiler/brw_ir_fs.h @@ -355,10 +355,43 @@ public: unsigned components_read(unsigned i) const; unsigned size_read(int arg) const; bool can_do_source_mods(const struct intel_device_info *devinfo) const; - bool can_do_cmod(); + bool can_do_cmod() const; bool can_change_types() const; bool has_source_and_destination_hazard() const; + bool is_3src(const struct brw_compiler *compiler) const; + bool is_math() const; + bool is_control_flow_begin() const; + bool is_control_flow_end() const; + bool is_control_flow() const; + bool is_commutative() const; + bool can_do_saturate() const; + bool reads_accumulator_implicitly() const; + bool writes_accumulator_implicitly(const struct intel_device_info *devinfo) const; + + /** + * Instructions that use indirect addressing have additional register + * regioning restrictions. + */ + bool uses_indirect_addressing() const; + + void remove(bblock_t *block, bool defer_later_block_ip_updates = false); + void insert_after(bblock_t *block, fs_inst *inst); + void insert_before(bblock_t *block, fs_inst *inst); + + /** + * True if the instruction has side effects other than writing to + * its destination registers. You are expected not to reorder or + * optimize these out unless you know what you are doing. + */ + bool has_side_effects() const; + + /** + * True if the instruction might be affected by side effects of other + * instructions. + */ + bool is_volatile() const; + /** * Return whether \p arg is a control source of a virtual instruction which * shouldn't contribute to the execution type and usual regioning diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index bc631450bdd..0ea53ccd616 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -298,7 +298,7 @@ backend_reg::is_accumulator() const } bool -backend_instruction::is_commutative() const +fs_inst::is_commutative() const { switch (opcode) { case BRW_OPCODE_AND: @@ -322,13 +322,13 @@ backend_instruction::is_commutative() const } bool -backend_instruction::is_3src(const struct brw_compiler *compiler) const +fs_inst::is_3src(const struct brw_compiler *compiler) const { return ::is_3src(&compiler->isa, opcode); } bool -backend_instruction::is_math() const +fs_inst::is_math() const { return (opcode == SHADER_OPCODE_RCP || opcode == SHADER_OPCODE_RSQ || @@ -343,7 +343,7 @@ backend_instruction::is_math() const } bool -backend_instruction::is_control_flow_begin() const +fs_inst::is_control_flow_begin() const { switch (opcode) { case BRW_OPCODE_DO: @@ -356,7 +356,7 @@ backend_instruction::is_control_flow_begin() const } bool -backend_instruction::is_control_flow_end() const +fs_inst::is_control_flow_end() const { switch (opcode) { case BRW_OPCODE_ELSE: @@ -369,7 +369,7 @@ backend_instruction::is_control_flow_end() const } bool -backend_instruction::is_control_flow() const +fs_inst::is_control_flow() const { switch (opcode) { case BRW_OPCODE_DO: @@ -386,7 +386,7 @@ backend_instruction::is_control_flow() const } bool -backend_instruction::uses_indirect_addressing() const +fs_inst::uses_indirect_addressing() const { switch (opcode) { case SHADER_OPCODE_BROADCAST: @@ -399,36 +399,7 @@ backend_instruction::uses_indirect_addressing() const } bool -backend_instruction::can_do_source_mods() const -{ - switch (opcode) { - case BRW_OPCODE_ADDC: - case BRW_OPCODE_BFE: - case BRW_OPCODE_BFI1: - case BRW_OPCODE_BFI2: - case BRW_OPCODE_BFREV: - case BRW_OPCODE_CBIT: - case BRW_OPCODE_FBH: - case BRW_OPCODE_FBL: - case BRW_OPCODE_ROL: - case BRW_OPCODE_ROR: - case BRW_OPCODE_SUBB: - case BRW_OPCODE_DP4A: - case BRW_OPCODE_DPAS: - case SHADER_OPCODE_BROADCAST: - case SHADER_OPCODE_CLUSTER_BROADCAST: - case SHADER_OPCODE_MOV_INDIRECT: - case SHADER_OPCODE_SHUFFLE: - case SHADER_OPCODE_INT_QUOTIENT: - case SHADER_OPCODE_INT_REMAINDER: - return false; - default: - return true; - } -} - -bool -backend_instruction::can_do_saturate() const +fs_inst::can_do_saturate() const { switch (opcode) { case BRW_OPCODE_ADD: @@ -473,52 +444,7 @@ backend_instruction::can_do_saturate() const } bool -backend_instruction::can_do_cmod() const -{ - switch (opcode) { - case BRW_OPCODE_ADD: - case BRW_OPCODE_ADD3: - case BRW_OPCODE_ADDC: - case BRW_OPCODE_AND: - case BRW_OPCODE_ASR: - case BRW_OPCODE_AVG: - case BRW_OPCODE_CMP: - case BRW_OPCODE_CMPN: - case BRW_OPCODE_DP2: - case BRW_OPCODE_DP3: - case BRW_OPCODE_DP4: - case BRW_OPCODE_DPH: - case BRW_OPCODE_FRC: - case BRW_OPCODE_LINE: - case BRW_OPCODE_LRP: - case BRW_OPCODE_LZD: - case BRW_OPCODE_MAC: - case BRW_OPCODE_MACH: - case BRW_OPCODE_MAD: - case BRW_OPCODE_MOV: - case BRW_OPCODE_MUL: - case BRW_OPCODE_NOT: - case BRW_OPCODE_OR: - case BRW_OPCODE_PLN: - case BRW_OPCODE_RNDD: - case BRW_OPCODE_RNDE: - case BRW_OPCODE_RNDU: - case BRW_OPCODE_RNDZ: - case BRW_OPCODE_SAD2: - case BRW_OPCODE_SADA2: - case BRW_OPCODE_SHL: - case BRW_OPCODE_SHR: - case BRW_OPCODE_SUBB: - case BRW_OPCODE_XOR: - case FS_OPCODE_LINTERP: - return true; - default: - return false; - } -} - -bool -backend_instruction::reads_accumulator_implicitly() const +fs_inst::reads_accumulator_implicitly() const { switch (opcode) { case BRW_OPCODE_MAC: @@ -531,7 +457,7 @@ backend_instruction::reads_accumulator_implicitly() const } bool -backend_instruction::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const +fs_inst::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const { return writes_accumulator || (opcode == FS_OPCODE_LINTERP && !devinfo->has_pln) || @@ -539,7 +465,7 @@ backend_instruction::writes_accumulator_implicitly(const struct intel_device_inf } bool -backend_instruction::has_side_effects() const +fs_inst::has_side_effects() const { switch (opcode) { case SHADER_OPCODE_SEND: @@ -575,7 +501,7 @@ backend_instruction::has_side_effects() const } bool -backend_instruction::is_volatile() const +fs_inst::is_volatile() const { switch (opcode) { case SHADER_OPCODE_SEND: @@ -622,7 +548,7 @@ adjust_later_block_ips(bblock_t *start_block, int ip_adjustment) } void -backend_instruction::insert_after(bblock_t *block, backend_instruction *inst) +fs_inst::insert_after(bblock_t *block, fs_inst *inst) { assert(this != inst); assert(block->end_ip_delta == 0); @@ -638,7 +564,7 @@ backend_instruction::insert_after(bblock_t *block, backend_instruction *inst) } void -backend_instruction::insert_before(bblock_t *block, backend_instruction *inst) +fs_inst::insert_before(bblock_t *block, fs_inst *inst) { assert(this != inst); assert(block->end_ip_delta == 0); @@ -654,7 +580,7 @@ backend_instruction::insert_before(bblock_t *block, backend_instruction *inst) } void -backend_instruction::remove(bblock_t *block, bool defer_later_block_ip_updates) +fs_inst::remove(bblock_t *block, bool defer_later_block_ip_updates) { assert(inst_is_in_block(block, this) || !"Instruction not in block");