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radv: precompute existing legacy GS register values later

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To precompute all registers at the same place.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29022>
This commit is contained in:
Samuel Pitoiset
2024-05-02 15:00:13 +02:00
committed by Marge Bot
parent 88dfe04b08
commit e5bc4d85bb
6 changed files with 44 additions and 19 deletions
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src/amd/vulkan/nir/radv_nir_lower_abi.c
+1 -1
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@@ -287,7 +287,7 @@ lower_abi_instr(nir_builder *b, nir_intrinsic_instr *intrin, void *state)
replacement = ac_nir_load_arg(b, &s->args->ac, s->args->vgt_esgs_ring_itemsize);
} else {
const unsigned stride =
s->info->is_ngg ? s->info->ngg_info.vgt_esgs_ring_itemsize : s->info->gs_ring_info.vgt_esgs_ring_itemsize;
s->info->is_ngg ? s->info->ngg_info.vgt_esgs_ring_itemsize : s->info->gs_ring_info.esgs_itemsize;
replacement = nir_imm_int(b, stride);
}
break;