From e5970fe22a66bf1727d8b677f4e3c93fe2172a71 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 20 Jun 2022 17:31:06 +0200 Subject: [PATCH] nir/lower_task_shader: don't use base index for shared memory intrinsics MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel backend doesn't handle them very well. Fixes: 8aff8d3dd42 ("nir: Add common task shader lowering to make the backend's job easier.") Reviewed-by: Marcin Ślusarz Part-of: --- src/compiler/nir/nir_lower_task_shader.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/compiler/nir/nir_lower_task_shader.c b/src/compiler/nir/nir_lower_task_shader.c index 6d7040828fe..1417cbdea44 100644 --- a/src/compiler/nir/nir_lower_task_shader.c +++ b/src/compiler/nir/nir_lower_task_shader.c @@ -55,8 +55,7 @@ lower_nv_task_output(nir_builder *b, case nir_intrinsic_load_output: { b->cursor = nir_after_instr(instr); nir_ssa_def *load = - nir_load_shared(b, 1, 32, nir_imm_int(b, 0), - .base = s->task_count_shared_addr); + nir_load_shared(b, 1, 32, nir_imm_int(b, s->task_count_shared_addr)); nir_ssa_def_rewrite_uses(&intrin->dest.ssa, load); nir_instr_remove(instr); return true; @@ -65,8 +64,7 @@ lower_nv_task_output(nir_builder *b, case nir_intrinsic_store_output: { b->cursor = nir_after_instr(instr); nir_ssa_def *store_val = intrin->src[0].ssa; - nir_store_shared(b, store_val, nir_imm_int(b, 0), - .base = s->task_count_shared_addr); + nir_store_shared(b, store_val, nir_imm_int(b, s->task_count_shared_addr)); nir_instr_remove(instr); return true; } @@ -86,7 +84,7 @@ append_launch_mesh_workgroups_to_nv_task(nir_builder *b, */ b->cursor = nir_before_cf_list(&b->impl->body); nir_ssa_def *zero = nir_imm_int(b, 0); - nir_store_shared(b, zero, zero, .base = s->task_count_shared_addr); + nir_store_shared(b, zero, nir_imm_int(b, s->task_count_shared_addr)); nir_scoped_barrier(b, .execution_scope = NIR_SCOPE_WORKGROUP, @@ -106,7 +104,7 @@ append_launch_mesh_workgroups_to_nv_task(nir_builder *b, .memory_modes = nir_var_mem_shared); nir_ssa_def *task_count = - nir_load_shared(b, 1, 32, zero, .base = s->task_count_shared_addr); + nir_load_shared(b, 1, 32, nir_imm_int(b, s->task_count_shared_addr)); /* NV_mesh_shader doesn't offer to choose which task_payload variable * should be passed to mesh shaders, we just pass all.