From e58f28f3dadf236896979a56c69f879d27067154 Mon Sep 17 00:00:00 2001 From: Danylo Piliaiev Date: Fri, 3 Feb 2023 12:00:21 +0100 Subject: [PATCH] ir3: Make FS tex prefetch optimization optional a610 and friends seem not to have tex prefetch. Signed-off-by: Danylo Piliaiev Part-of: --- src/freedreno/common/freedreno_dev_info.h | 2 ++ src/freedreno/common/freedreno_devices.py | 2 ++ src/freedreno/ir3/ir3_compiler.c | 2 ++ src/freedreno/ir3/ir3_compiler.h | 2 ++ src/freedreno/ir3/ir3_context.c | 2 +- 5 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h index f05c130ae49..e5d0ae07770 100644 --- a/src/freedreno/common/freedreno_dev_info.h +++ b/src/freedreno/common/freedreno_dev_info.h @@ -72,6 +72,8 @@ struct fd_dev_info { bool has_hw_multiview; + bool has_fs_tex_prefetch; + /* Whether the PC_MULTIVIEW_MASK register exists. */ bool supports_multiview_mask; diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index cfe91086564..1e09cc3630e 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -153,6 +153,7 @@ class A6xxGPUInfo(GPUInfo): self.a6xx.has_gmem_fast_clear = True self.a6xx.has_hw_multiview = True + self.a6xx.has_fs_tex_prefetch = True self.a6xx.sysmem_per_ccu_cache_size = 64 * 1024 self.a6xx.gmem_ccu_color_cache_fraction = CCUColorCacheFraction.QUARTER.value @@ -248,6 +249,7 @@ a6xx_gen1 = dict( a6xx_gen1_low = {**a6xx_gen1, **dict( has_gmem_fast_clear = False, has_hw_multiview = False, + has_fs_tex_prefetch = False, sysmem_per_ccu_cache_size = 8 * 1024, gmem_ccu_color_cache_fraction = CCUColorCacheFraction.HALF.value, vs_max_inputs_count = 16, diff --git a/src/freedreno/ir3/ir3_compiler.c b/src/freedreno/ir3/ir3_compiler.c index 272a30883db..37d2bec56ff 100644 --- a/src/freedreno/ir3/ir3_compiler.c +++ b/src/freedreno/ir3/ir3_compiler.c @@ -204,6 +204,8 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id, compiler->shared_consts_base_offset = 504; compiler->shared_consts_size = 8; compiler->geom_shared_consts_size_quirk = 16; + + compiler->has_fs_tex_prefetch = dev_info->a6xx.has_fs_tex_prefetch; } else { compiler->max_const_pipeline = 512; compiler->max_const_geom = 512; diff --git a/src/freedreno/ir3/ir3_compiler.h b/src/freedreno/ir3/ir3_compiler.h index 77360a8435b..1730fa40809 100644 --- a/src/freedreno/ir3/ir3_compiler.h +++ b/src/freedreno/ir3/ir3_compiler.h @@ -237,6 +237,8 @@ struct ir3_compiler { * TODO: Keep an eye on this for next gens. */ uint64_t geom_shared_consts_size_quirk; + + bool has_fs_tex_prefetch; }; void ir3_compiler_destroy(struct ir3_compiler *compiler); diff --git a/src/freedreno/ir3/ir3_context.c b/src/freedreno/ir3/ir3_context.c index e58bedde966..6f8f7384484 100644 --- a/src/freedreno/ir3/ir3_context.c +++ b/src/freedreno/ir3/ir3_context.c @@ -123,7 +123,7 @@ ir3_context_init(struct ir3_compiler *compiler, struct ir3_shader *shader, /* Enable the texture pre-fetch feature only a4xx onwards. But * only enable it on generations that have been tested: */ - if ((so->type == MESA_SHADER_FRAGMENT) && (compiler->gen >= 6)) + if ((so->type == MESA_SHADER_FRAGMENT) && compiler->has_fs_tex_prefetch) NIR_PASS_V(ctx->s, ir3_nir_lower_tex_prefetch); NIR_PASS(progress, ctx->s, nir_lower_phis_to_scalar, true);