From e3b794c184c6eba584030f277a263aedbd6e8127 Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Thu, 15 Sep 2022 15:41:59 -0700 Subject: [PATCH] iris: Drop the RT flush for PIPE_BARRIER_TEXTURE The render target flush would have been needed if it was possible to: 1) pollute the render cache and write to the data port in one draw call. 2) perform a subsequent operation that assumed the render cache was up-to-date. However, this is not possible for the two glMemoryBarrier barrier bits that get translated to this pipe barrier: * GL_TEXTURE_FETCH_BARRIER_BIT is only used for sampling operations. It's possible to pollute the render cache and data cache with writes to a texture in one draw call (1). However, the GL spec states that apps cannot assume that any existing render caches are up-to-date for sampling the written locations immediately afterwards. Apps are required to use glTextureBarrier before the sampling operation, so requirement #2 is not satisfied. * GL_PIXEL_BUFFER_BARRIER_BIT could be used for a PBO upload (2), but it's not possible to pollute the render cache and data cache with a PBO access in one draw call. PBOs cannot be bound to framebuffers for rendering, so requirement #1 is not satisfied. Reviewed-by: Lionel Landwerlin (v1) Reviewed-by: Francisco Jerez Part-of: --- src/gallium/drivers/iris/iris_pipe_control.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c index a424320a8b6..fe35a6f6a84 100644 --- a/src/gallium/drivers/iris/iris_pipe_control.c +++ b/src/gallium/drivers/iris/iris_pipe_control.c @@ -409,7 +409,16 @@ iris_memory_barrier(struct pipe_context *ctx, unsigned flags) PIPE_CONTROL_CONST_CACHE_INVALIDATE; } - if (flags & (PIPE_BARRIER_TEXTURE | PIPE_BARRIER_FRAMEBUFFER)) { + if (flags & PIPE_BARRIER_TEXTURE) + bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; + + if (flags & PIPE_BARRIER_FRAMEBUFFER) { + /* The caller may have issued a render target read and a data cache data + * port write in the same draw call. Depending on the hardware, iris + * performs render target reads with either the sampler or the render + * cache data port. If the next framebuffer access is a render target + * read, the previously affected caches must be invalidated. + */ bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_RENDER_TARGET_FLUSH; }