diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c index af9e9f8d55b..9825a94410d 100644 --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c @@ -49,6 +49,8 @@ struct apply_pipeline_layout_state { const struct anv_physical_device *pdevice; + struct anv_pipeline_bind_map *bind_map; + const struct anv_pipeline_sets_layout *layout; nir_address_format desc_addr_format; nir_address_format ssbo_addr_format; @@ -213,6 +215,18 @@ add_tex_src_binding(struct apply_pipeline_layout_state *state, struct anv_binding_apply_layout *layout = add_deref_src_binding(state, tex->src[deref_src_idx].src); + /* Track input attachments use */ + nir_variable *var = + nir_deref_instr_get_variable( + nir_src_as_deref(tex->src[deref_src_idx].src)); + if (var->data.fb_fetch_output) { + assert(var->data.index == NIR_VARIABLE_NO_INDEX || + var->data.index < MAX_DESCRIPTOR_SET_INPUT_ATTACHMENTS); + const uint32_t index = var->data.index == NIR_VARIABLE_NO_INDEX ? + MAX_DESCRIPTOR_SET_INPUT_ATTACHMENTS : var->data.index; + BITSET_SET(state->bind_map->input_attachments, index); + } + /* This is likely a fallout of Wa_14020375314 but hasn't fully be * understood by HW people yet. * @@ -2547,6 +2561,7 @@ anv_nir_apply_pipeline_layout(nir_shader *shader, struct apply_pipeline_layout_state state = { .mem_ctx = ralloc_context(NULL), .pdevice = pdevice, + .bind_map = map, .layout = layout, .desc_addr_format = bindless_stage ? nir_address_format_64bit_global_32bit_offset : diff --git a/src/intel/vulkan/anv_physical_device.c b/src/intel/vulkan/anv_physical_device.c index 69dfd426a36..ae6d2eaed70 100644 --- a/src/intel/vulkan/anv_physical_device.c +++ b/src/intel/vulkan/anv_physical_device.c @@ -946,7 +946,6 @@ get_features(const struct anv_physical_device *pdevice, #define MAX_PER_STAGE_DESCRIPTOR_UNIFORM_BUFFERS 64 #define MAX_PER_STAGE_DESCRIPTOR_INPUT_ATTACHMENTS 64 -#define MAX_DESCRIPTOR_SET_INPUT_ATTACHMENTS 256 static VkDeviceSize anx_get_physical_device_max_heap_size(const struct anv_physical_device *pdevice) diff --git a/src/intel/vulkan/anv_pipeline_cache.c b/src/intel/vulkan/anv_pipeline_cache.c index 46eb21d51fa..a3dd2e35ddf 100644 --- a/src/intel/vulkan/anv_pipeline_cache.c +++ b/src/intel/vulkan/anv_pipeline_cache.c @@ -383,6 +383,10 @@ anv_shader_bin_create(struct anv_device *device, bind_map->embedded_sampler_count); shader->bind_map.embedded_sampler_to_binding = embedded_sampler_to_binding; + typed_memcpy(shader->bind_map.input_attachments, + bind_map->input_attachments, + ARRAY_SIZE(bind_map->input_attachments)); + typed_memcpy(kernel_args, bind_map->kernel_args, bind_map->kernel_arg_count); shader->bind_map.kernel_args = kernel_args; @@ -457,6 +461,8 @@ anv_shader_bin_serialize(struct vk_pipeline_cache_object *object, blob_write_bytes(blob, shader->bind_map.embedded_sampler_to_binding, shader->bind_map.embedded_sampler_count * sizeof(*shader->bind_map.embedded_sampler_to_binding)); + blob_write_bytes(blob, shader->bind_map.input_attachments, + sizeof(shader->bind_map.input_attachments)); blob_write_bytes(blob, shader->bind_map.kernel_args, shader->bind_map.kernel_arg_count * sizeof(*shader->bind_map.kernel_args)); @@ -529,6 +535,8 @@ anv_shader_bin_deserialize(struct vk_pipeline_cache *cache, bind_map.embedded_sampler_to_binding = (void *) blob_read_bytes(blob, bind_map.embedded_sampler_count * sizeof(*bind_map.embedded_sampler_to_binding)); + blob_copy_bytes(blob, bind_map.input_attachments, + sizeof(bind_map.input_attachments)); bind_map.kernel_args = (void *) blob_read_bytes(blob, bind_map.kernel_arg_count * sizeof(*bind_map.kernel_args)); diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index c1104c59211..15f7ad94293 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -181,6 +181,7 @@ struct intel_perf_query_result; #define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32 #define MAX_EMBEDDED_SAMPLERS 2048 #define MAX_CUSTOM_BORDER_COLORS 4096 +#define MAX_DESCRIPTOR_SET_INPUT_ATTACHMENTS 256 /* We need 16 for UBO block reads to work and 32 for push UBOs. However, we * use 64 here to avoid cache issues. This could most likely bring it back to * 32 if we had different virtual addresses for the different views on a given @@ -4690,6 +4691,7 @@ struct anv_pipeline_bind_map { struct anv_pipeline_binding * surface_to_descriptor; struct anv_pipeline_binding * sampler_to_descriptor; struct anv_pipeline_embedded_sampler_binding* embedded_sampler_to_binding; + BITSET_DECLARE(input_attachments, MAX_DESCRIPTOR_SET_INPUT_ATTACHMENTS + 1); struct brw_kernel_arg_desc * kernel_args; struct anv_push_range push_ranges[4]; @@ -4934,8 +4936,6 @@ struct anv_graphics_pipeline { uint32_t view_mask; uint32_t instance_multiplier; - bool rp_has_ds_self_dep; - bool kill_pixel; bool uses_xfb; bool sample_shading_enable; diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c index ca105e144d3..fb8ec99f270 100644 --- a/src/intel/vulkan/genX_gfx_state.c +++ b/src/intel/vulkan/genX_gfx_state.c @@ -271,12 +271,24 @@ static const uint32_t vk_to_intel_shading_rate_combiner_op[] = { #endif static bool -has_ds_feedback_loop(const struct vk_dynamic_graphics_state *dyn) +has_ds_feedback_loop(const struct anv_pipeline_bind_map *bind_map, + const struct vk_dynamic_graphics_state *dyn) { - return (dyn->feedback_loops & (VK_IMAGE_ASPECT_DEPTH_BIT | - VK_IMAGE_ASPECT_STENCIL_BIT)) || - dyn->ial.depth_att != MESA_VK_ATTACHMENT_UNUSED || - dyn->ial.stencil_att != MESA_VK_ATTACHMENT_UNUSED; + if (BITSET_IS_EMPTY(bind_map->input_attachments)) + return false; + + const unsigned depth_att = dyn->ial.depth_att == MESA_VK_ATTACHMENT_NO_INDEX ? + MAX_DESCRIPTOR_SET_INPUT_ATTACHMENTS : dyn->ial.depth_att; + const unsigned stencil_att = dyn->ial.stencil_att == MESA_VK_ATTACHMENT_NO_INDEX ? + MAX_DESCRIPTOR_SET_INPUT_ATTACHMENTS : dyn->ial.stencil_att; + + return + (dyn->feedback_loops & (VK_IMAGE_ASPECT_DEPTH_BIT | + VK_IMAGE_ASPECT_STENCIL_BIT)) != 0 || + (dyn->ial.depth_att != MESA_VK_ATTACHMENT_UNUSED && + BITSET_TEST(bind_map->input_attachments, depth_att)) || + (dyn->ial.stencil_att != MESA_VK_ATTACHMENT_UNUSED && + BITSET_TEST(bind_map->input_attachments, stencil_att)); } UNUSED static bool @@ -392,9 +404,10 @@ want_stencil_pma_fix(const struct vk_dynamic_graphics_state *dyn, * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable) || * (3DSTATE_PS_EXTRA::Pixel Shader Computed Depth mode != PSCDEPTH_OFF) */ + struct anv_shader_bin *fs_bin = pipeline->base.shaders[MESA_SHADER_FRAGMENT]; + return pipeline->kill_pixel || - pipeline->rp_has_ds_self_dep || - has_ds_feedback_loop(dyn) || + has_ds_feedback_loop(&fs_bin->bind_map, dyn) || wm_prog_data->computed_depth_mode != PSCDEPTH_OFF; } @@ -906,12 +919,13 @@ update_ps_extra_kills_pixel(struct anv_gfx_dynamic_state *hw_state, const struct anv_cmd_graphics_state *gfx, const struct anv_graphics_pipeline *pipeline) { + struct anv_shader_bin *fs_bin = pipeline->base.shaders[MESA_SHADER_FRAGMENT]; const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline); SET_STAGE(PS_EXTRA, ps_extra.PixelShaderKillsPixel, - wm_prog_data && (pipeline->rp_has_ds_self_dep || - has_ds_feedback_loop(dyn) || - wm_prog_data->uses_kill), + wm_prog_data && + (has_ds_feedback_loop(&fs_bin->bind_map, dyn) || + wm_prog_data->uses_kill), FRAGMENT); } diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index dab5a840e0b..d4cd8ec900f 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -1711,11 +1711,7 @@ compute_kill_pixel(struct anv_graphics_pipeline *pipeline, * 3DSTATE_PS_BLEND::AlphaTestEnable since Vulkan doesn't have a concept * of an alpha test. */ - pipeline->rp_has_ds_self_dep = - (state->pipeline_flags & - VK_PIPELINE_CREATE_2_DEPTH_STENCIL_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT) != 0; pipeline->kill_pixel = - pipeline->rp_has_ds_self_dep || wm_prog_data->uses_kill || wm_prog_data->uses_omask || (ms && ms->alpha_to_coverage_enable);