From e28195bf4b0e928ae16fe09f6a076bef4c719c60 Mon Sep 17 00:00:00 2001 From: Ruijing Dong Date: Mon, 15 Apr 2024 19:18:57 -0400 Subject: [PATCH] radeonsi/vcn: enable decoding in vcn5. Signed-off-by: David (Ming Qiang) Wu Signed-off-by: Ruijing Dong Reviewed-by: Leo Liu Acked-by: Pierre-Eric Pelloux-Prayer OA# Part-of: --- src/amd/common/ac_vcn_dec.h | 6 ++++ src/gallium/drivers/radeonsi/radeon_vcn_dec.c | 32 ++++++++++++++++--- src/gallium/drivers/radeonsi/radeon_vcn_dec.h | 4 +++ 3 files changed, 38 insertions(+), 4 deletions(-) diff --git a/src/amd/common/ac_vcn_dec.h b/src/amd/common/ac_vcn_dec.h index 65eaabfa0a6..459cd9c4cd6 100644 --- a/src/amd/common/ac_vcn_dec.h +++ b/src/amd/common/ac_vcn_dec.h @@ -112,6 +112,7 @@ #define RDECODE_VC1_PROFILE_ADVANCED 0x00000002 #define RDECODE_SW_MODE_LINEAR 0x00000000 +/* for legacy VCN generations */ #define RDECODE_256B_S 0x00000001 #define RDECODE_256B_D 0x00000002 #define RDECODE_4KB_S 0x00000005 @@ -122,6 +123,8 @@ #define RDECODE_4KB_D_X 0x00000016 #define RDECODE_64KB_S_X 0x00000019 #define RDECODE_64KB_D_X 0x0000001A +/* for VCN5 */ +#define RDECODE_VCN5_256B_D 0x00000001 #define RDECODE_MESSAGE_NOT_SUPPORTED 0x00000000 #define RDECODE_MESSAGE_CREATE 0x00000001 @@ -855,6 +858,7 @@ typedef struct rvcn_dec_message_hevc_s { unsigned char direct_reflist[2][15]; unsigned int st_rps_bits; + unsigned char reserved_1[15]; } rvcn_dec_message_hevc_t; typedef struct rvcn_dec_message_vp9_s { @@ -896,6 +900,7 @@ typedef struct rvcn_dec_message_vp9_s { unsigned int vp9_frame_size; unsigned int compressed_header_size; unsigned int uncompressed_header_size; + unsigned char reserved[2]; } rvcn_dec_message_vp9_t; typedef enum { @@ -1026,6 +1031,7 @@ typedef struct rvcn_dec_message_av1_s { unsigned int uncompressed_header_size; rvcn_dec_warped_motion_params_t global_motion[8]; rvcn_dec_av1_tile_info_t tile_info[256]; + unsigned char reserved[3]; } rvcn_dec_message_av1_t; typedef struct rvcn_dec_feature_index_s { diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_dec.c b/src/gallium/drivers/radeonsi/radeon_vcn_dec.c index 3b5f89f9f0f..26baec00e4b 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_dec.c +++ b/src/gallium/drivers/radeonsi/radeon_vcn_dec.c @@ -1816,7 +1816,7 @@ static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn height = align(decode->height_in_samples, dec->db_alignment); size = align((width * height * 3) / 2, 256); if (dec->ref_codec.bts == CODEC_10_BITS) - size = size * 3 / 2; + size = dec->dpb_version == DPB_VERSION_VCN5 ? size * 2 : size * 3 / 2; list_for_each_entry_safe(struct rvcn_dec_dynamic_dpb_t2, d, &dec->dpb_ref_list, list) { for (i = 0; i < dec->ref_codec.ref_size; ++i) { @@ -1895,7 +1895,6 @@ static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn addr = dec->ws->buffer_get_virtual_address(dpb->dpb.res->buf); dynamic_dpb_t2->dpbCurrLo = addr; dynamic_dpb_t2->dpbCurrHi = addr >> 32; - decode->decode_flags = 1; dynamic_dpb_t2->dpbConfigFlags = 0; dynamic_dpb_t2->dpbLumaPitch = align(decode->width_in_samples, dec->db_alignment); @@ -1908,8 +1907,13 @@ static unsigned rvcn_dec_dynamic_dpb_t2_message(struct radeon_decoder *dec, rvcn dynamic_dpb_t2->dpbChromaAlignedHeight * 2; if (dec->ref_codec.bts == CODEC_10_BITS) { - dynamic_dpb_t2->dpbLumaAlignedSize = dynamic_dpb_t2->dpbLumaAlignedSize * 3 / 2; - dynamic_dpb_t2->dpbChromaAlignedSize = dynamic_dpb_t2->dpbChromaAlignedSize * 3 / 2; + if (dec->dpb_version == DPB_VERSION_VCN5) { + dynamic_dpb_t2->dpbLumaAlignedSize = dynamic_dpb_t2->dpbLumaAlignedSize * 2; + dynamic_dpb_t2->dpbChromaAlignedSize = dynamic_dpb_t2->dpbChromaAlignedSize * 2; + } else { + dynamic_dpb_t2->dpbLumaAlignedSize = dynamic_dpb_t2->dpbLumaAlignedSize * 3 / 2; + dynamic_dpb_t2->dpbChromaAlignedSize = dynamic_dpb_t2->dpbChromaAlignedSize * 3 / 2; + } } return 0; @@ -2204,6 +2208,8 @@ static struct pb_buffer_lean *rvcn_dec_message_decode(struct radeon_decoder *dec decode->dt_field_mode = ((struct vl_video_buffer *)out_surf)->base.interlaced; decode->dt_surf_tile_config = 0; decode->dt_uv_surf_tile_config = 0; + if (dec->dpb_version == DPB_VERSION_VCN5) + decode->db_swizzle_mode = RDECODE_VCN5_256B_D; decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; @@ -2974,6 +2980,7 @@ static void radeon_dec_end_frame(struct pipe_video_codec *decoder, struct pipe_v flush(dec, picture->flush_flags, picture->fence); if (picture->fence) dec->ws->fence_reference(dec->ws, &dec->prev_fence, *picture->fence); + next_buffer(dec); } @@ -3256,6 +3263,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, dec->addr_gfx_mode = RDECODE_ARRAY_MODE_LINEAR; dec->av1_version = RDECODE_AV1_VER_0; + dec->dpb_version = DPB_VERSION_LEGACY; switch (sctx->vcn_ip_ver) { case VCN_1_0_0: @@ -3304,11 +3312,27 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context, dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11; dec->av1_version = RDECODE_AV1_VER_1; break; + case VCN_5_0_0: + dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V3; + dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11; + dec->av1_version = RDECODE_AV1_VER_1; + dec->dpb_version = DPB_VERSION_VCN5; + break; default: RVID_ERR("VCN is not supported.\n"); goto error; } + /* hack for vcn 5 temporarily */ + if (sctx->vcn_ip_ver >= VCN_5_0_0) { + if (stream_type == RDECODE_CODEC_VP9 || + stream_type == RDECODE_CODEC_AV1 || + stream_type == RDECODE_CODEC_H265) + dec->db_alignment = 64; + else if(stream_type == RDECODE_CODEC_H264_PERF) + dec->db_alignment = 256; + } + if (dec->stream_type != RDECODE_CODEC_JPEG) { map_msg_fb_it_probs_buf(dec); rvcn_dec_message_create(dec); diff --git a/src/gallium/drivers/radeonsi/radeon_vcn_dec.h b/src/gallium/drivers/radeonsi/radeon_vcn_dec.h index a8d099d28ad..91ee4a4e4d4 100644 --- a/src/gallium/drivers/radeonsi/radeon_vcn_dec.h +++ b/src/gallium/drivers/radeonsi/radeon_vcn_dec.h @@ -97,6 +97,10 @@ struct radeon_decoder { unsigned h264_valid_ref_num[17]; unsigned h264_valid_poc_num[34]; unsigned av1_version; + enum { + DPB_VERSION_LEGACY = 0, + DPB_VERSION_VCN5 + } dpb_version; bool show_frame; unsigned ref_idx; bool tmz_ctx;