diff --git a/src/amd/compiler/aco_builder_h.py b/src/amd/compiler/aco_builder_h.py index f96b7b665be..b1054bda76f 100644 --- a/src/amd/compiler/aco_builder_h.py +++ b/src/amd/compiler/aco_builder_h.py @@ -365,7 +365,7 @@ public: assert(tmp.type() == RegType::sgpr && tmp.bytes() <= 8); % endif Operand op(tmp); - op.setFixed(aco::${fixed}); + op.setPrecolored(aco::${fixed}); return op; } @@ -374,7 +374,7 @@ public: //vcc_hi and exec_hi can still be used in wave32 assert(def.regClass().type() == RegType::sgpr && def.bytes() <= 8); % endif - def.setFixed(aco::${fixed}); + def.setPrecolored(aco::${fixed}); return def; } diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 8b4bb1f8bcf..0d233131232 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -10837,7 +10837,7 @@ begin_uniform_if_then(isel_context* ctx, if_context* ic, Temp cond) branch.reset(create_instruction(branch_opcode, Format::PSEUDO_BRANCH, 1, 1)); branch->definitions[0] = Definition(ctx->program->allocateTmp(s2)); branch->operands[0] = Operand(cond); - branch->operands[0].setFixed(scc); + branch->operands[0].setPrecolored(scc); ctx->block->instructions.emplace_back(std::move(branch)); ic->BB_if_idx = ctx->block->index; @@ -11307,7 +11307,7 @@ create_fs_jump_to_epilog(isel_context* ctx) chan = Operand(tmp); } - chan.setFixed(chan_reg); + chan.setPrecolored(chan_reg); exports.emplace_back(chan); } } @@ -11455,7 +11455,7 @@ add_startpgm(struct isel_context* ctx) } else { Temp dst = ctx->program->allocateTmp(type); Definition def(dst); - def.setFixed(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256}); + def.setPrecolored(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256}); ctx->arg_temps[i] = dst; startpgm->definitions[arg++] = def; @@ -11471,11 +11471,11 @@ add_startpgm(struct isel_context* ctx) Temp idy = ctx->program->allocateTmp(s1); ctx->ttmp8 = ctx->program->allocateTmp(s1); startpgm->definitions[def_count - 3] = Definition(idx); - startpgm->definitions[def_count - 3].setFixed(PhysReg(108 + 9 /*ttmp9*/)); + startpgm->definitions[def_count - 3].setPrecolored(PhysReg(108 + 9 /*ttmp9*/)); startpgm->definitions[def_count - 2] = Definition(ctx->ttmp8); - startpgm->definitions[def_count - 2].setFixed(PhysReg(108 + 8 /*ttmp8*/)); + startpgm->definitions[def_count - 2].setPrecolored(PhysReg(108 + 8 /*ttmp8*/)); startpgm->definitions[def_count - 1] = Definition(idy); - startpgm->definitions[def_count - 1].setFixed(PhysReg(108 + 7 /*ttmp7*/)); + startpgm->definitions[def_count - 1].setPrecolored(PhysReg(108 + 7 /*ttmp7*/)); ctx->workgroup_id[0] = Operand(idx); if (ctx->args->workgroup_ids[2].used) { Builder bld(ctx->program, ctx->block); @@ -11913,7 +11913,7 @@ create_merged_jump_to_epilog(isel_context* ctx) const unsigned reg = ctx->args->args[i].offset; Operand op(ctx->arg_temps[i]); - op.setFixed(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256}); + op.setPrecolored(PhysReg{file == AC_ARG_SGPR ? reg : reg + 256}); regs.emplace_back(op); } diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp index a2741eb2af9..2c0b17a82ca 100644 --- a/src/amd/compiler/aco_ir.cpp +++ b/src/amd/compiler/aco_ir.cpp @@ -346,11 +346,11 @@ convert_to_SDWA(amd_gfx_level gfx_level, aco_ptr& instr) sdwa.dst_sel = SubdwordSel(instr->definitions[0].bytes(), 0, false); if (instr->definitions[0].getTemp().type() == RegType::sgpr && gfx_level == GFX8) - instr->definitions[0].setFixed(vcc); + instr->definitions[0].setPrecolored(vcc); if (instr->definitions.size() >= 2) - instr->definitions[1].setFixed(vcc); + instr->definitions[1].setPrecolored(vcc); if (instr->operands.size() >= 3) - instr->operands[2].setFixed(vcc); + instr->operands[2].setPrecolored(vcc); instr->pass_flags = tmp->pass_flags; @@ -474,11 +474,11 @@ convert_to_DPP(amd_gfx_level gfx_level, aco_ptr& instr, bool dpp8) instr->valu().opsel_hi = tmp->valu().opsel_hi; if ((instr->isVOPC() || instr->definitions.size() > 1) && gfx_level < GFX11) - instr->definitions.back().setFixed(vcc); + instr->definitions.back().setPrecolored(vcc); if (instr->operands.size() >= 3 && instr->operands[2].isOfType(RegType::sgpr) && gfx_level < GFX11) - instr->operands[2].setFixed(vcc); + instr->operands[2].setPrecolored(vcc); instr->pass_flags = tmp->pass_flags; diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index 085188a8619..9fe200f5977 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -473,7 +473,7 @@ public: assert(r.id()); /* Don't allow fixing an undef to a register */ data_.temp = r; isTemp_ = true; - setFixed(reg); + setPrecolored(reg); }; /* 8-bit constant */ @@ -919,7 +919,7 @@ public: {} explicit Definition(Temp tmp) noexcept : temp(tmp) {} explicit Definition(PhysReg reg, RegClass type) noexcept : temp(Temp(0, type)) { setFixed(reg); } - explicit Definition(Temp tmp, PhysReg reg) noexcept : temp(tmp) { setFixed(reg); } + explicit Definition(Temp tmp, PhysReg reg) noexcept : temp(tmp) { setPrecolored(reg); } constexpr bool isTemp() const noexcept { return tempId() > 0; } diff --git a/src/amd/compiler/aco_optimizer_postRA.cpp b/src/amd/compiler/aco_optimizer_postRA.cpp index e250837dee9..58f68cc00a8 100644 --- a/src/amd/compiler/aco_optimizer_postRA.cpp +++ b/src/amd/compiler/aco_optimizer_postRA.cpp @@ -404,7 +404,8 @@ try_optimize_scc_nocompare(pr_opt_ctx& ctx, aco_ptr& instr) /* Use the SCC def from wr_instr */ ctx.uses[instr->operands[0].tempId()]--; - instr->operands[0] = Operand(wr_instr->definitions[1].getTemp(), scc); + instr->operands[0] = Operand(wr_instr->definitions[1].getTemp()); + instr->operands[0].setFixed(scc); ctx.uses[instr->operands[0].tempId()]++; /* Set the opcode and operand to 32-bit */ diff --git a/src/amd/compiler/aco_register_allocation.cpp b/src/amd/compiler/aco_register_allocation.cpp index 198fe6e74c7..2c60f6a0a9c 100644 --- a/src/amd/compiler/aco_register_allocation.cpp +++ b/src/amd/compiler/aco_register_allocation.cpp @@ -2117,7 +2117,8 @@ handle_fixed_operands(ra_ctx& ctx, RegisterFile& register_file, BITSET_SET(mask, i); - Operand pc_op(instr->operands[i].getTemp(), src); + Operand pc_op(instr->operands[i].getTemp()); + pc_op.setFixed(src); Definition pc_def = Definition(op.physReg(), pc_op.regClass()); parallelcopy.emplace_back(pc_op, pc_def); } @@ -3095,7 +3096,7 @@ register_allocation(Program* program, ra_test_policy policy) /* v_writelane_b32 can take two sgprs but only if one is m0. */ if (ctx.assignments[instr->operands[0].tempId()].reg != m0 && ctx.assignments[instr->operands[1].tempId()].reg != m0) { - instr->operands[0].setFixed(m0); + instr->operands[0].setPrecolored(m0); fixed = true; } } @@ -3137,7 +3138,7 @@ register_allocation(Program* program, ra_test_policy policy) */ int op_fixed_to_def = get_op_fixed_to_def(instr.get()); if (op_fixed_to_def != -1) - instr->definitions[0].setFixed(instr->operands[op_fixed_to_def].physReg()); + instr->definitions[0].setPrecolored(instr->operands[op_fixed_to_def].physReg()); /* handle fixed definitions first */ for (unsigned i = 0; i < instr->definitions.size(); ++i) { diff --git a/src/amd/compiler/tests/test_regalloc.cpp b/src/amd/compiler/tests/test_regalloc.cpp index 1b878c2f46d..5902b780ca7 100644 --- a/src/amd/compiler/tests/test_regalloc.cpp +++ b/src/amd/compiler/tests/test_regalloc.cpp @@ -76,7 +76,7 @@ BEGIN_TEST(regalloc.precolor.swap) //! s2: %op0_2:s[2-3], s2: %op1_2:s[0-1] = p_parallelcopy %op0:s[0-1], %op1:s[2-3] //! p_unit_test %op0_2:s[2-3], %op1_2:s[0-1] Operand op(inputs[0]); - op.setFixed(PhysReg(2)); + op.setPrecolored(PhysReg(2)); bld.pseudo(aco_opcode::p_unit_test, op, op1); finish_ra_test(ra_test_policy()); @@ -90,7 +90,7 @@ BEGIN_TEST(regalloc.precolor.blocking_vector) //! s1: %tmp1_2:s[1], s2: %tmp0_2:s[2-3] = p_parallelcopy %tmp1:s[2], %tmp0:s[0-1] //! p_unit_test %tmp1_2:s[1] Operand op(inputs[1]); - op.setFixed(PhysReg(1)); + op.setPrecolored(PhysReg(1)); bld.pseudo(aco_opcode::p_unit_test, op); //! p_unit_test %tmp0_2:s[2-3] @@ -107,7 +107,7 @@ BEGIN_TEST(regalloc.precolor.vector.test) //! s2: %tmp0_2:s[2-3], s1: %tmp2_2:s[#t2] = p_parallelcopy %tmp0:s[0-1], %tmp2:s[3] //! p_unit_test %tmp0_2:s[2-3] Operand op(inputs[0]); - op.setFixed(PhysReg(2)); + op.setPrecolored(PhysReg(2)); bld.pseudo(aco_opcode::p_unit_test, op); //! p_unit_test %tmp2_2:s[#t2] @@ -124,7 +124,7 @@ BEGIN_TEST(regalloc.precolor.vector.collect) //! s2: %tmp0_2:s[2-3], s1: %tmp1_2:s[#t1], s1: %tmp2_2:s[#t2] = p_parallelcopy %tmp0:s[0-1], %tmp1:s[2], %tmp2:s[3] //! p_unit_test %tmp0_2:s[2-3] Operand op(inputs[0]); - op.setFixed(PhysReg(2)); + op.setPrecolored(PhysReg(2)); bld.pseudo(aco_opcode::p_unit_test, op); //! p_unit_test %tmp1_2:s[#t1], %tmp2_2:s[#t2]