From e2644a138944696098e25640390437efb687578d Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Fri, 21 Nov 2025 15:25:36 +0100 Subject: [PATCH] radv: only reset SPM when cache counters are enabled with RGP Otherwise, it's not necessary. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_sqtt.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_sqtt.c b/src/amd/vulkan/radv_sqtt.c index bb586df6080..7f14cf827f0 100644 --- a/src/amd/vulkan/radv_sqtt.c +++ b/src/amd/vulkan/radv_sqtt.c @@ -498,9 +498,9 @@ radv_begin_sqtt(struct radv_queue *queue) /* Enable SQG events that collects thread trace data. */ ac_emit_cp_spi_config_cntl(cs.b, pdev->info.gfx_level, true); - radv_perfcounter_emit_reset(&cs, true); - if (device->spm.bo) { + radv_perfcounter_emit_reset(&cs, true); + /* Enable all shader stages by default. */ radv_perfcounter_emit_shaders(device, &cs, ac_sqtt_get_shader_mask(&pdev->info)); @@ -580,7 +580,8 @@ radv_end_sqtt(struct radv_queue *queue) /* Stop SQTT. */ radv_emit_sqtt_stop(device, &cs); - radv_perfcounter_emit_reset(&cs, true); + if (device->spm.bo) + radv_perfcounter_emit_reset(&cs, true); /* Restore previous state by disabling SQG events. */ ac_emit_cp_spi_config_cntl(cs.b, pdev->info.gfx_level, false);