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aco: don't use divergence information for most ALU defs

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If one of the sources are divergent but all are SGPRs, then this can
cause issues (for example, imul with two SGPR sources and a VGPR definition).

No fossil-db changes (navi21)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12454
Backport-to: 24.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32997>
This commit is contained in:
Rhys Perry
2024-04-10 17:23:40 +01:00
committed by Marge Bot
parent cd5c135349
commit e18e293e6c
1 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/compiler/aco_instruction_selection_setup.cpp
+9 -9
View File
@@ -397,7 +397,7 @@ init_context(isel_context* ctx, nir_shader* shader)
switch (instr->type) {
case nir_instr_type_alu: {
nir_alu_instr* alu_instr = nir_instr_as_alu(instr);
RegType type = alu_instr->def.divergent ? RegType::vgpr : RegType::sgpr;
RegType type = RegType::sgpr;
/* packed 16bit instructions have to be VGPR */
if (alu_instr->def.num_components == 2 &&
@@ -409,13 +409,11 @@ init_context(isel_context* ctx, nir_shader* shader)
case nir_op_f2u16:
case nir_op_f2i32:
case nir_op_f2u32:
case nir_op_b2i8:
case nir_op_b2i16:
case nir_op_b2i32:
case nir_op_b2b32:
case nir_op_b2f16:
case nir_op_b2f32:
case nir_op_mov: break;
case nir_op_mov:
if (alu_instr->def.divergent &&
regclasses[alu_instr->src[0].src.ssa->index].type() == RegType::vgpr)
type = RegType::vgpr;
break;
case nir_op_fmulz:
case nir_op_ffmaz:
case nir_op_f2f64:
@@ -486,7 +484,9 @@ init_context(isel_context* ctx, nir_shader* shader)
}
default:
for (unsigned i = 0; i < nir_op_infos[alu_instr->op].num_inputs; i++) {
if (regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr)
if (alu_instr->src[i].src.ssa->bit_size == 1
? nir_src_is_divergent(&alu_instr->src[i].src)
: regclasses[alu_instr->src[i].src.ssa->index].type() == RegType::vgpr)
type = RegType::vgpr;
}
break;