From e10e74a7af5ad0dac6cee7e930a73cb8d71252d6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Mon, 1 Feb 2021 16:25:13 +0100 Subject: [PATCH] aco: Implement new buffer load/store intrinsics. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Part-of: --- .../compiler/aco_instruction_selection.cpp | 49 +++++++++++++++++++ .../aco_instruction_selection_setup.cpp | 1 + 2 files changed, 50 insertions(+) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 888359ff5a3..9b8df55388d 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -6897,6 +6897,49 @@ void visit_global_atomic(isel_context *ctx, nir_intrinsic_instr *instr) } } +void visit_load_buffer(isel_context *ctx, nir_intrinsic_instr *intrin) +{ + Builder bld(ctx->program, ctx->block); + + Temp dst = get_ssa_temp(ctx, &intrin->dest.ssa); + Temp descriptor = bld.as_uniform(get_ssa_temp(ctx, intrin->src[0].ssa)); + Temp v_offset = as_vgpr(ctx, get_ssa_temp(ctx, intrin->src[1].ssa)); + Temp s_offset = bld.as_uniform(get_ssa_temp(ctx, intrin->src[2].ssa)); + + bool swizzled = nir_intrinsic_is_swizzled(intrin); + bool reorder = nir_intrinsic_can_reorder(intrin); + bool slc = nir_intrinsic_slc_amd(intrin); + + unsigned const_offset = nir_intrinsic_base(intrin); + unsigned elem_size_bytes = intrin->dest.ssa.bit_size / 8u; + unsigned num_components = intrin->dest.ssa.num_components; + unsigned swizzle_element_size = swizzled ? (ctx->program->chip_class <= GFX8 ? 4 : 16) : 0; + + load_vmem_mubuf(ctx, dst, descriptor, v_offset, s_offset, const_offset, + elem_size_bytes, num_components, swizzle_element_size, !swizzled, reorder, slc); +} + +void visit_store_buffer(isel_context *ctx, nir_intrinsic_instr *intrin) +{ + Temp store_src = get_ssa_temp(ctx, intrin->src[0].ssa); + Temp descriptor = get_ssa_temp(ctx, intrin->src[1].ssa); + Temp v_offset = get_ssa_temp(ctx, intrin->src[2].ssa); + Temp s_offset = get_ssa_temp(ctx, intrin->src[3].ssa); + + bool swizzled = nir_intrinsic_is_swizzled(intrin); + bool slc = nir_intrinsic_slc_amd(intrin); + + unsigned const_offset = nir_intrinsic_base(intrin); + unsigned write_mask = nir_intrinsic_write_mask(intrin); + unsigned elem_size_bytes = intrin->src[0].ssa->bit_size / 8u; + + nir_variable_mode mem_mode = nir_intrinsic_memory_modes(intrin); + memory_sync_info sync(mem_mode == nir_var_shader_out ? storage_vmem_output : storage_none); + + store_vmem_mubuf(ctx, store_src, descriptor, v_offset, s_offset, const_offset, + elem_size_bytes, write_mask, !swizzled, sync, slc); +} + sync_scope translate_nir_scope(nir_scope scope) { switch (scope) { @@ -8061,6 +8104,12 @@ void visit_intrinsic(isel_context *ctx, nir_intrinsic_instr *instr) case nir_intrinsic_load_global: visit_load_global(ctx, instr); break; + case nir_intrinsic_load_buffer_amd: + visit_load_buffer(ctx, instr); + break; + case nir_intrinsic_store_buffer_amd: + visit_store_buffer(ctx, instr); + break; case nir_intrinsic_store_global: visit_store_global(ctx, instr); break; diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 08b9e4d3c7a..3c34b4b0039 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -852,6 +852,7 @@ void init_context(isel_context *ctx, nir_shader *shader) case nir_intrinsic_load_scratch: case nir_intrinsic_load_invocation_id: case nir_intrinsic_load_primitive_id: + case nir_intrinsic_load_buffer_amd: type = RegType::vgpr; break; case nir_intrinsic_shuffle: