diff --git a/src/gallium/drivers/radeonsi/ci/gfx10-navi10-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx10-navi10-fail.csv index de39e3505a7..1c4f1a231be 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx10-navi10-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx10-navi10-fail.csv @@ -26,10 +26,6 @@ spec@oes_shader_io_blocks@compiler@layout-location-aliasing.vert,Fail spec@khr_texture_compression_astc@miptree-gles srgb-fp,Fail spec@khr_texture_compression_astc@miptree-gles srgb-fp@sRGB decode full precision,Fail -# glcts failures -GTF-GL46.gtf30.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_multisample,Fail -GTF-GL46.gtf32.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_32_multisample,Fail - # These are GLCTS bugs. See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10361 GTF-GL46.gtf31.GL3Tests.uniform_buffer_object.uniform_buffer_object_accessing_info_for_block_with_an_instance_array,Fail GTF-GL46.gtf31.GL3Tests.uniform_buffer_object.uniform_buffer_object_getactiveuniformblockiv,Fail diff --git a/src/gallium/drivers/radeonsi/ci/gfx10_3-navi21-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx10_3-navi21-fail.csv index f5c4e01754f..07cc8f11319 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx10_3-navi21-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx10_3-navi21-fail.csv @@ -29,8 +29,6 @@ spec@oes_shader_io_blocks@compiler@layout-location-aliasing.vert,Fail spec@arb_bindless_texture@compiler@samplers@arith-bound-sampler-texture2d.frag,Crash # glcts failures -GTF-GL46.gtf30.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_multisample,Fail -GTF-GL46.gtf32.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_32_multisample,Fail KHR-GL46.shader_image_load_store.basic-allTargets-atomic,Fail ## Fail because GFX10+ removed MS texture support (see si_get_sparse_texture_virtual_page_size) KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation,Fail diff --git a/src/gallium/drivers/radeonsi/ci/gfx11-navi31-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx11-navi31-fail.csv index 1db89527f35..da2594800a2 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx11-navi31-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx11-navi31-fail.csv @@ -29,8 +29,6 @@ spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail # glcts failures -GTF-GL46.gtf30.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_multisample,Fail -GTF-GL46.gtf32.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_32_multisample,Fail KHR-GL46.shaders.uniform_block.random.nested_structs_instance_arrays.0,Fail ## Fail because GFX10+ removed MS texture support (see si_get_sparse_texture_virtual_page_size) KHR-GL46.sparse_texture2_tests.SparseTexture2Allocation_texture_2d_multisample_array_r11f_g11f_b10f,Fail diff --git a/src/gallium/drivers/radeonsi/ci/gfx6-tahiti-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx6-tahiti-fail.csv index c7ed499eac9..47d73d97d48 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx6-tahiti-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx6-tahiti-fail.csv @@ -143,8 +143,6 @@ spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGBA2- swizzled- border spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGBA4- swizzled- border color only,Fail spec@!opengl 1.1@texwrap formats bordercolor-swizzled@GL_RGBA8- swizzled- border color only,Fail -GTF-GL46.gtf30.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_multisample,Fail -GTF-GL46.gtf32.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_32_multisample,Fail GTF-GL46.gtf32.GL3Tests.packed_pixels.packed_pixels,Fail GTF-GL46.gtf32.GL3Tests.packed_pixels.packed_pixels_pbo,Fail GTF-GL46.gtf32.GL3Tests.packed_pixels.packed_pixels_pixelstore,Fail diff --git a/src/gallium/drivers/radeonsi/ci/gfx7-hawaii-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx7-hawaii-fail.csv index 80282446cc6..0780b883881 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx7-hawaii-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx7-hawaii-fail.csv @@ -154,8 +154,6 @@ KHR-GL46.geometry_shader.layered_rendering_fbo_no_attachment.layered_rendering_f KHR-GL46.shader_image_load_store.advanced-sso-subroutine,Fail KHR-GL46.shader_image_load_store.basic-allTargets-atomic,Fail KHR-GL46.texture_cube_map_array.sampling,Fail -GTF-GL46.gtf30.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_multisample,Fail -GTF-GL46.gtf32.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_32_multisample,Fail # These are GLCTS bugs. See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10361 GTF-GL46.gtf31.GL3Tests.uniform_buffer_object.uniform_buffer_object_accessing_info_for_block_with_an_instance_array,Fail diff --git a/src/gallium/drivers/radeonsi/ci/gfx8-polaris11-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx8-polaris11-fail.csv index 17fb5938133..ef37f4b6124 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx8-polaris11-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx8-polaris11-fail.csv @@ -138,10 +138,6 @@ spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp,Fail spec@khr_texture_compression_astc@sliced-3d-miptree-gles srgb-fp@sRGB decode full precision,Fail spec@oes_shader_io_blocks@compiler@layout-location-aliasing.vert,Fail -# glcts failures -GTF-GL46.gtf30.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_multisample,Fail -GTF-GL46.gtf32.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_32_multisample,Fail - # These are GLCTS bugs. See: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10361 GTF-GL46.gtf31.GL3Tests.uniform_buffer_object.uniform_buffer_object_accessing_info_for_block_with_an_instance_array,Fail GTF-GL46.gtf31.GL3Tests.uniform_buffer_object.uniform_buffer_object_getactiveuniformblockiv,Fail diff --git a/src/gallium/drivers/radeonsi/ci/gfx9-vega20-fail.csv b/src/gallium/drivers/radeonsi/ci/gfx9-vega20-fail.csv index 9ed81f7bd3a..3beffc6461f 100644 --- a/src/gallium/drivers/radeonsi/ci/gfx9-vega20-fail.csv +++ b/src/gallium/drivers/radeonsi/ci/gfx9-vega20-fail.csv @@ -51,8 +51,6 @@ wgl@wgl-multi-window-single-context,Fail wgl@wgl-sanity,Fail # glcts failures -GTF-GL46.gtf30.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_multisample,Fail -GTF-GL46.gtf32.GL3Tests.fragment_coord_conventions.fragment_coord_conventions_32_multisample,Fail KHR-GL46.direct_state_access.framebuffers_texture_attachment,Fail KHR-GL46.direct_state_access.framebuffers_texture_layer_attachment,Fail KHR-GL46.geometry_shader.rendering.rendering.triangles_with_adjacency_input_line_strip_output_triangle_strip_adjacency_drawcall,Fail diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c b/src/gallium/drivers/radeonsi/si_gfx_cs.c index 85af4a2f2a8..2465c599d24 100644 --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c @@ -309,7 +309,6 @@ void si_set_tracked_regs_to_clear_state(struct si_context *ctx) ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_Z_FORMAT] = 0; ctx->tracked_regs.reg_value[SI_TRACKED_SPI_SHADER_COL_FORMAT] = 0; - ctx->tracked_regs.reg_value[SI_TRACKED_SPI_BARYC_CNTL] = 0; ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ENA] = 0; ctx->tracked_regs.reg_value[SI_TRACKED_SPI_PS_INPUT_ADDR] = 0; diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index d00b9ad9087..fe87d276842 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -2309,6 +2309,7 @@ static bool run_pre_link_optimization_passes(struct si_nir_shader_ctx *ctx) .load_sample_positions_always_loads_current_ones = true, .force_front_face = key->ps.opt.force_front_face_input, .optimize_frag_coord = true, + .frag_coord_is_center = true, /* This does a lot of things. See the description in ac_nir_lower_ps_early_options. */ .ps_iter_samples = key->ps.part.prolog.samplemask_log_ps_iter ? (1 << key->ps.part.prolog.samplemask_log_ps_iter) : @@ -2348,6 +2349,7 @@ static bool run_pre_link_optimization_passes(struct si_nir_shader_ctx *ctx) } else { ac_nir_lower_ps_early_options early_options = { .optimize_frag_coord = true, + .frag_coord_is_center = true, .alpha_func = COMPARE_FUNC_ALWAYS, .spi_shader_col_format_hint = ~0, }; diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index c426712cebe..d2b4056f737 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -1022,7 +1022,6 @@ struct si_shader { struct { unsigned spi_ps_input_ena; unsigned spi_ps_input_addr; - unsigned spi_baryc_cntl; unsigned spi_ps_in_control; unsigned spi_shader_z_format; unsigned spi_shader_col_format; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 4b9ad217ecc..a60d76d7ccf 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4983,8 +4983,10 @@ static void gfx6_init_gfx_preamble_state(struct si_context *sctx) /* Graphics registers. */ si_init_graphics_preamble_state(sctx, pm4); - if (!has_clear_state) + if (!has_clear_state) { ac_pm4_set_reg(&pm4->base, R_02800C_DB_RENDER_OVERRIDE, 0); + ac_pm4_set_reg(&pm4->base, R_0286E0_SPI_BARYC_CNTL, 0); + } if (sctx->family >= CHIP_POLARIS10 && !sctx->screen->info.has_small_prim_filter_sample_loc_bug) { /* Polaris10-12 should disable small line culling, but those also have the sample loc bug, @@ -5141,6 +5143,7 @@ static void gfx12_init_gfx_preamble_state(struct si_context *sctx) ac_pm4_set_reg(&pm4->base, R_028648_SPI_SHADER_IDX_FORMAT, S_028648_IDX0_EXPORT_FORMAT(V_028648_SPI_SHADER_1COMP)); + ac_pm4_set_reg(&pm4->base, R_028658_SPI_BARYC_CNTL, 0); /* The rate combiners have no effect if they are disabled like this: * VERTEX_RATE: BYPASS_VTX_RATE_COMBINER = 1 diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h index 2869aa717b4..60ac3c14908 100644 --- a/src/gallium/drivers/radeonsi/si_state.h +++ b/src/gallium/drivers/radeonsi/si_state.h @@ -309,9 +309,10 @@ enum si_tracked_reg /* 5 consecutive registers (GFX12), or 2 consecutive registers (GFX6-11) */ SI_TRACKED_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_COL_FORMAT, - /* Continuing consecutive registers (GFX12), or separate register (GFX6-11) */ - SI_TRACKED_SPI_BARYC_CNTL, - /* Continuing consecutive registers (GFX12), or 2 consecutive registers (GFX6-11) */ + + SI_TRACKED__UNUSED_GAP, /* TODO: remove */ + + /* 2 consecutive registers. */ SI_TRACKED_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ADDR, diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.cpp b/src/gallium/drivers/radeonsi/si_state_shaders.cpp index f2c886a4be3..ab97ad26a4c 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.cpp +++ b/src/gallium/drivers/radeonsi/si_state_shaders.cpp @@ -2012,8 +2012,6 @@ static void gfx6_emit_shader_ps(struct si_context *sctx, unsigned index) radeon_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA, shader->ps.spi_ps_input_ena, shader->ps.spi_ps_input_addr); - radeon_opt_set_context_reg(R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL, - shader->ps.spi_baryc_cntl); radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL, shader->ps.spi_ps_in_control); radeon_opt_set_context_reg2(R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT, @@ -2034,8 +2032,6 @@ static void gfx11_dgpu_emit_shader_ps(struct si_context *sctx, unsigned index) shader->ps.spi_ps_input_ena); gfx11_opt_set_context_reg(R_0286D0_SPI_PS_INPUT_ADDR, SI_TRACKED_SPI_PS_INPUT_ADDR, shader->ps.spi_ps_input_addr); - gfx11_opt_set_context_reg(R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL, - shader->ps.spi_baryc_cntl); gfx11_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL, shader->ps.spi_ps_in_control); gfx11_opt_set_context_reg(R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT, @@ -2060,8 +2056,6 @@ static void gfx12_emit_shader_ps(struct si_context *sctx, unsigned index) shader->ps.spi_shader_z_format); gfx12_opt_set_context_reg(R_028654_SPI_SHADER_COL_FORMAT, SI_TRACKED_SPI_SHADER_COL_FORMAT, shader->ps.spi_shader_col_format); - gfx12_opt_set_context_reg(R_028658_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL, - shader->ps.spi_baryc_cntl); gfx12_opt_set_context_reg(R_02865C_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA, shader->ps.spi_ps_input_ena); gfx12_opt_set_context_reg(R_028660_SPI_PS_INPUT_ADDR, SI_TRACKED_SPI_PS_INPUT_ADDR, @@ -2190,27 +2184,6 @@ static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader) if (sscreen->info.has_rbplus && !sscreen->info.rbplus_allowed) shader->ps.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1); - /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION - * Possible values: - * 0 -> Position = pixel center - * 1 -> Position = pixel centroid - * 2 -> Position = at sample position - * - * From GLSL 4.5 specification, section 7.1: - * "The variable gl_FragCoord is available as an input variable from - * within fragment shaders and it holds the window relative coordinates - * (x, y, z, 1/w) values for the fragment. If multi-sampling, this - * value can be for any location within the pixel, or one of the - * fragment samples. The use of centroid does not further restrict - * this value to be inside the current primitive." - * - * Meaning that centroid has no effect and we can return anything within - * the pixel. Thus, return the value at sample position, because that's - * the most accurate one shaders can get. - */ - shader->ps.spi_baryc_cntl = S_0286E0_POS_FLOAT_LOCATION(2) | - S_0286E0_POS_FLOAT_ULC(info->base.fs.pixel_center_integer) | - S_0286E0_FRONT_FACE_ALL_BITS(0); shader->ps.spi_shader_col_format = si_get_spi_shader_col_format(shader); shader->ps.cb_shader_mask = ac_get_cb_shader_mask(shader->key.ps.part.epilog.spi_shader_col_format); shader->ps.spi_ps_input_ena = shader->config.spi_ps_input_ena;