From e0bec58340dc8bf63de71764e5eeae24d98d487d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timur=20Krist=C3=B3f?= Date: Fri, 13 May 2022 16:13:54 +0200 Subject: [PATCH] radv: Fix loading task shader ring buffer addresses. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I forgot to use task_ring_offsets instead of ring_offsets when I ported this code to the new ABI. Fixes: a8bdcf3c92b12bb551e11bebaf23fa7802f01075 Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Reviewed-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_nir_lower_abi.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c index 249aa57e44a..3b5cdd8a296 100644 --- a/src/amd/vulkan/radv_nir_lower_abi.c +++ b/src/amd/vulkan/radv_nir_lower_abi.c @@ -39,7 +39,12 @@ typedef struct { static nir_ssa_def * load_ring(nir_builder *b, unsigned ring, lower_abi_state *s) { - nir_ssa_def *ring_offsets = ac_nir_load_arg(b, &s->args->ac, s->args->ring_offsets); + struct ac_arg arg = + b->shader->info.stage == MESA_SHADER_TASK ? + s->args->task_ring_offsets : + s->args->ring_offsets; + + nir_ssa_def *ring_offsets = ac_nir_load_arg(b, &s->args->ac, arg); ring_offsets = nir_pack_64_2x32_split(b, nir_channel(b, ring_offsets, 0), nir_channel(b, ring_offsets, 1)); return nir_load_smem_amd(b, 4, ring_offsets, nir_imm_int(b, ring * 16u), .align_mul = 4u); }