diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 15b94e04e2f..946b58aabc0 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2894,9 +2894,7 @@ emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shad
       rsrc1_reg = R_00B328_SPI_SHADER_PGM_RSRC1_ES;
    }
 
-   radeon_set_sh_reg_seq(cmd_buffer->cs, pgm_lo_reg, 2);
-   radeon_emit(cmd_buffer->cs, prolog_va >> 8);
-   radeon_emit(cmd_buffer->cs, S_00B124_MEM_BASE(prolog_va >> 40));
+   radeon_set_sh_reg(cmd_buffer->cs, pgm_lo_reg, prolog_va >> 8);
 
    if (chip < GFX10)
       radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1);
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 37218715bc9..567d857eaae 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -310,6 +310,9 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
                         S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
    }
 
+   radeon_set_sh_reg(cs, R_00B124_SPI_SHADER_PGM_HI_VS,
+                     S_00B124_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
+
    unsigned cu_mask_ps = 0xffffffff;
 
    /* It's wasteful to enable all CUs for PS if shader arrays have a