diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c
index 08b9b55cc9a..8ae3eb399d1 100644
--- a/src/gallium/drivers/iris/iris_clear.c
+++ b/src/gallium/drivers/iris/iris_clear.c
@@ -522,8 +522,8 @@ fast_clear_depth(struct iris_context *ice,
 
       /* Also set the indirect clear color if it exists. */
       if (res->aux.clear_color_bo) {
-         uint32_t packed_depth;
-         isl_color_value_pack(&clear_value, res->surf.format, &packed_depth);
+         uint32_t packed_depth[4] = {};
+         isl_color_value_pack(&clear_value, res->surf.format, packed_depth);
 
          const uint64_t clear_pixel_offset = res->aux.clear_color_offset +
             isl_get_sampler_clear_field_offset(devinfo, res->surf.format);
@@ -531,7 +531,7 @@ fast_clear_depth(struct iris_context *ice,
          iris_emit_pipe_control_write(batch, "update fast clear value (Z)",
                                       PIPE_CONTROL_WRITE_IMMEDIATE,
                                       res->aux.clear_color_bo,
-                                      clear_pixel_offset, packed_depth);
+                                      clear_pixel_offset, packed_depth[0]);
 
          /* From the TGL PRMs, Volume 9: Render Engine, State Caching :
           *
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 84797522d25..8b15626c9db 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -476,8 +476,8 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
       const union isl_color_value clear_value =
          anv_image_hiz_clear_value(image);
 
-      uint32_t depth_value;
-      isl_color_value_pack(&clear_value, depth_format, &depth_value);
+      uint32_t depth_value[4] = {};
+      isl_color_value_pack(&clear_value, depth_format, depth_value);
 
       const uint32_t clear_pixel_offset = clear_color_addr.offset +
          isl_get_sampler_clear_field_offset(cmd_buffer->device->info,
@@ -490,7 +490,7 @@ transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
       struct mi_builder b;
       mi_builder_init(&b, cmd_buffer->device->info, &cmd_buffer->batch);
       mi_builder_set_write_check(&b, true);
-      mi_store(&b, mi_mem32(clear_pixel_addr), mi_imm(depth_value));
+      mi_store(&b, mi_mem32(clear_pixel_addr), mi_imm(depth_value[0]));
    }
 
    /* If will_full_fast_clear is set, the caller promises to fast-clear the