aco/tests: add more VALUMaskWriteHazard tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30818>
This commit is contained in:
Rhys Perry
@@ -1116,7 +1116,7 @@ BEGIN_TEST(insert_nops.valu_mask_write)
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bld.sopp(aco_opcode::s_waitcnt_depctr, 0xfffe);
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(2), s1), Operand(PhysReg(1), s1));
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/* Instruction which is both involved in the hazard and is a mitigation. */
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/* v_cndmask_b32 is both involved in the hazard and is a mitigation. */
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//! p_unit_test 4
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//! v1: %0:v[0] = v_cndmask_b32 %0:s[2], 0, %0:s[0-1]
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//! s1: %0:s[1] = s_mov_b32 0
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@@ -1128,6 +1128,156 @@ BEGIN_TEST(insert_nops.valu_mask_write)
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(1), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(2), s1), Operand(PhysReg(1), s1));
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/* VALU reading exec does not mitigate the hazard. We also don't consider literals. */
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//! p_unit_test 5
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[0-1]
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//! v1: %0:v[1] = v_mov_b32 %0:exec_lo
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//! s1: %0:s[1] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[2] = s_mov_b32 %0:s[1]
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bld.pseudo(aco_opcode::p_unit_test, Operand::c32(5));
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(0), s2));
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bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg(257), v1), Operand(exec_lo, s1));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(1), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(2), s1), Operand(PhysReg(1), s1));
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//! p_unit_test 6
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[0-1]
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//! v1: %0:v[1] = v_mov_b32 0x200
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//! s1: %0:s[1] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[2] = s_mov_b32 %0:s[1]
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bld.pseudo(aco_opcode::p_unit_test, Operand::c32(6));
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(0), s2));
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bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg(257), v1), Operand::literal32(0x200));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(1), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(2), s1), Operand(PhysReg(1), s1));
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/* Basic case: VALU. */
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//! p_unit_test 7
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[0-1]
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//! s1: %0:s[1] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! v1: %0:v[1] = v_mov_b32 %0:s[1]
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bld.pseudo(aco_opcode::p_unit_test, Operand::c32(7));
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(0), s2));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(1), s1), Operand::zero());
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bld.vop1(aco_opcode::v_mov_b32, Definition(PhysReg(257), v1), Operand(PhysReg(1), s1));
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/* SALU which both reads and writes a lane mask SGPR. */
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//! p_unit_test 8
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[0-1]
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//! s1: %0:s[1] = s_mov_b32 0
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[2-3]
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[2] = s_mov_b32 %0:s[1]
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[4] = s_mov_b32 %0:s[2]
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bld.pseudo(aco_opcode::p_unit_test, Operand::c32(8));
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(0), s2));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(1), s1), Operand::zero());
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(2), s2));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(2), s1), Operand(PhysReg(1), s1));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(4), s1), Operand(PhysReg(2), s1));
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/* When a SALU writes a lane mask, we shouldn't forget the current SGPRs used as lane masks then
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* written. */
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//! p_unit_test 9
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[0-1]
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//! s1: %0:s[0] = s_mov_b32 0
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[2-3]
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//! s1: %0:s[2] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[4] = s_mov_b32 %0:s[0]
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//! s1: %0:s[5] = s_mov_b32 %0:s[2]
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bld.pseudo(aco_opcode::p_unit_test, Operand::c32(9));
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(0), s2));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(0), s1), Operand::zero());
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(2), s2));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(2), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(4), s1), Operand(PhysReg(0), s1));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(5), s1), Operand(PhysReg(2), s1));
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/* When a SALU writes a lane mask, we shouldn't forget all SGPRs used as lane masks, there might
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* be later problematic writes. */
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//! p_unit_test 10
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[0-1]
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//! s1: %0:s[0] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[4] = s_mov_b32 %0:s[0]
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//! s1: %0:s[1] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[5] = s_mov_b32 %0:s[1]
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bld.pseudo(aco_opcode::p_unit_test, Operand::c32(10));
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(0), s2));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(0), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(4), s1), Operand(PhysReg(0), s1));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(1), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(5), s1), Operand(PhysReg(1), s1));
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//! p_unit_test 11
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[0-1]
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//! s1: %0:s[0] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[4] = s_mov_b32 %0:s[0]
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//! s1: %0:s[0] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[5] = s_mov_b32 %0:s[0]
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bld.pseudo(aco_opcode::p_unit_test, Operand::c32(11));
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(0), s2));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(0), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(4), s1), Operand(PhysReg(0), s1));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(0), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(5), s1), Operand(PhysReg(0), s1));
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//! p_unit_test 12
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bld.pseudo(aco_opcode::p_unit_test, Operand::c32(12));
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//! BB1
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//! /* logical preds: / linear preds: BB0, / kind: */
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[0-1]
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bld.reset(program->create_and_insert_block());
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program->blocks[0].linear_succs.push_back(1);
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program->blocks[1].linear_preds.push_back(0);
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(0), s2));
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//! BB2
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//! /* logical preds: / linear preds: BB0, / kind: */
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//! v1: %0:v[0] = v_cndmask_b32 0, 0, %0:s[2-3]
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bld.reset(program->create_and_insert_block());
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program->blocks[0].linear_succs.push_back(2);
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program->blocks[2].linear_preds.push_back(0);
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bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(PhysReg(256), v1), Operand::zero(),
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Operand::zero(), Operand(PhysReg(2), s2));
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//! BB3
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//! /* logical preds: / linear preds: BB1, BB2, / kind: uniform, */
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//! s1: %0:s[0] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[4] = s_mov_b32 %0:s[0]
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//! s1: %0:s[2] = s_mov_b32 0
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//! s_waitcnt_depctr sa_sdst(0)
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//! s1: %0:s[5] = s_mov_b32 %0:s[2]
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bld.reset(program->create_and_insert_block());
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program->blocks[1].linear_succs.push_back(3);
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program->blocks[2].linear_succs.push_back(3);
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program->blocks[3].linear_preds.push_back(1);
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program->blocks[3].linear_preds.push_back(2);
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(0), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(4), s1), Operand(PhysReg(0), s1));
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(2), s1), Operand::zero());
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bld.sop1(aco_opcode::s_mov_b32, Definition(PhysReg(5), s1), Operand(PhysReg(2), s1));
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finish_insert_nops_test();
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END_TEST
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