From de7d8e53b72c6952e6ea16229cbcca28c141b56d Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Thu, 17 Jun 2021 09:39:50 -0700 Subject: [PATCH] iris: Emit clear_params as part of cso_z->packets This should be a bit faster. Reviewed-by: Kenneth Graunke Part-of: --- src/gallium/drivers/iris/iris_state.c | 63 +++++++++++++-------------- 1 file changed, 30 insertions(+), 33 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 75af879273a..7cdf8bca13e 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -6230,41 +6230,10 @@ iris_upload_dirty_render_state(struct iris_context *ice, if (dirty & IRIS_DIRTY_DEPTH_BUFFER) { struct iris_depth_buffer_state *cso_z = &ice->state.genx->depth_buffer; - /* Do not emit the clear params yets. We need to update the clear value - * first. - */ + /* Do not emit the cso yet. We may need to update clear params first. */ uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4; uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;; -#if GFX_VERx10 == 120 - /* Wa_14010455700 - * - * ISL will change some CHICKEN registers depending on the depth surface - * format, along with emitting the depth and stencil packets. In that - * case, we want to do a depth flush and stall, so the pipeline is not - * using these settings while we change the registers. - */ - iris_emit_end_of_pipe_sync(batch, - "Workaround: Stop pipeline for 14010455700", - PIPE_CONTROL_DEPTH_STALL | - PIPE_CONTROL_DEPTH_CACHE_FLUSH); -#endif - - iris_batch_emit(batch, cso_z->packets, cso_z_size); - if (GFX_VER >= 12) { - /* Wa_1408224581 - * - * Workaround: Gfx12LP Astep only An additional pipe control with - * post-sync = store dword operation would be required.( w/a is to - * have an additional pipe control after the stencil state whenever - * the surface state bits of this state is changing). - */ - iris_emit_pipe_control_write(batch, "WA for stencil state", - PIPE_CONTROL_WRITE_IMMEDIATE, - batch->screen->workaround_address.bo, - batch->screen->workaround_address.offset, 0); - } - union isl_color_value clear_value = { .f32 = { 0, } }; struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer; @@ -6281,7 +6250,35 @@ iris_upload_dirty_render_state(struct iris_context *ice, clear.DepthClearValueValid = true; clear.DepthClearValue = clear_value.f32[0]; } - iris_batch_emit(batch, clear_params, clear_length); + +#if GFX_VERx10 == 120 + /* Wa_14010455700 + * + * ISL will change some CHICKEN registers depending on the depth surface + * format, along with emitting the depth and stencil packets. In that + * case, we want to do a depth flush and stall, so the pipeline is not + * using these settings while we change the registers. + */ + iris_emit_end_of_pipe_sync(batch, + "Workaround: Stop pipeline for 14010455700", + PIPE_CONTROL_DEPTH_STALL | + PIPE_CONTROL_DEPTH_CACHE_FLUSH); +#endif + + iris_batch_emit(batch, cso_z->packets, batch->screen->isl_dev.ds.size); + if (GFX_VER >= 12) { + /* Wa_1408224581 + * + * Workaround: Gfx12LP Astep only An additional pipe control with + * post-sync = store dword operation would be required.( w/a is to + * have an additional pipe control after the stencil state whenever + * the surface state bits of this state is changing). + */ + iris_emit_pipe_control_write(batch, "WA for stencil state", + PIPE_CONTROL_WRITE_IMMEDIATE, + batch->screen->workaround_address.bo, + batch->screen->workaround_address.offset, 0); + } } if (dirty & (IRIS_DIRTY_DEPTH_BUFFER | IRIS_DIRTY_WM_DEPTH_STENCIL)) {