diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index bb585d5d4af..a77cd74169f 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1166,36 +1166,20 @@ to upconvert to 32b float internally?
Disable early z-test and early-lrz test (if applicable)
- A special mode that allows early-lrz test but disables
- early-z test. Which might sound a bit funny, since
- lrz-test happens before z-test. But as long as a couple
- conditions are maintained this allows using lrz-test in
- cases where fragment shader has kill/discard:
+ A special mode that allows early-lrz (if applicable) or early-z
+ tests, but also does late-z tests at which point it writes depth.
- 1) Disable lrz-write in cases where it is uncertain during
- binning pass that a fragment will pass. Ie. if frag
- shader has-kill, writes-z, or alpha/stencil test is
- enabled. (For correctness, lrz-write must be disabled
- when blend is enabled.) This is analogous to how a
- z-prepass works.
+ This mode is used when fragment can be killed (via discard or
+ sample mask) after early-z tests and it writes depth. In such case
+ depth can be written only at late-z stage, but it's ok to use
+ early-z to discard fragments.
- 2) Disable lrz-write and test if a depth-test direction
- reversal is detected. Due to condition (1), the contents
- of the lrz buffer are a conservative estimation of the
- depth buffer during the draw pass. Meaning that geometry
- that we know for certain will not be visible will not pass
- lrz-test. But geometry which may be (or contributes to
- blend) will pass the lrz-test.
-
- This allows us to keep early-lrz-test in cases where the frag
- shader does not write-z (ie. we know the z-value before FS)
- and does not have side-effects (image/ssbo writes, etc), but
- does have kill/discard. Which turns out to be a common
- enough case that it is useful to keep early-lrz test against
- the conservative lrz buffer to discard fragments that we
- know will definitely not be visible.
+ However this mode is not compatible with:
+ - Lack of D/S attachment
+ - Stencil writes on stencil or depth test failures
+ - Per-sample shading
-
+
Not a real hw value, used internally by mesa
@@ -3233,9 +3217,9 @@ to upconvert to 32b float internally?
-
+
-
+
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc
index fa9a6c407c6..bf59158861a 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.cc
+++ b/src/freedreno/vulkan/tu_cmd_buffer.cc
@@ -1251,8 +1251,8 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
phys_dev->info->a6xx.has_lrz_feedback
- ? (hw_binning ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z :
- LRZ_FEEDBACK_EARLY_LRZ_LATE_Z)
+ ? (hw_binning ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z :
+ LRZ_FEEDBACK_EARLY_Z_LATE_Z)
: LRZ_FEEDBACK_NONE,
});
@@ -2346,7 +2346,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
.buffers_location = BUFFERS_IN_SYSMEM,
.lrz_feedback_zmode_mask =
cmd->device->physical_device->info->a6xx.has_lrz_feedback
- ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z
+ ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
@@ -2452,7 +2452,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
phys_dev->info->a6xx.has_lrz_feedback
- ? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
+ ? LRZ_FEEDBACK_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE
});
@@ -6215,7 +6215,7 @@ tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_fs_reads_dynamic_ds_input_attachment(cmd, fs)) &&
(depth_write || stencil_write)) {
zmode = (cmd->state.lrz.valid && cmd->state.lrz.enabled)
- ? A6XX_EARLY_LRZ_LATE_Z
+ ? A6XX_EARLY_Z_LATE_Z
: A6XX_LATE_Z;
}
@@ -6234,7 +6234,7 @@ tu6_build_depth_plane_z_mode(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
*/
if (!force_late_z && cmd->state.lrz.enabled && fs->variant->writes_pos &&
zmode != A6XX_LATE_Z) {
- zmode = A6XX_EARLY_LRZ_LATE_Z;
+ zmode = A6XX_EARLY_Z_LATE_Z;
}
if ((force_late_z && !fs->variant->fs.early_fragment_tests) ||
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
index 13d7b95610c..e2b579bc691 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
@@ -98,7 +98,7 @@ compute_ztest_mode(struct fd6_emit *emit, bool lrz_valid) assert_dt
* that could discard samples that would otherwise only be
* hidden by a later draw.
*/
- return lrz_valid ? A6XX_EARLY_LRZ_LATE_Z : A6XX_LATE_Z;
+ return lrz_valid ? A6XX_EARLY_Z_LATE_Z : A6XX_LATE_Z;
} else {
return A6XX_EARLY_Z;
}
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
index 7cf9e35a9a0..cb3fe974ca7 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
@@ -1177,7 +1177,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
.force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = screen->info->a6xx.has_lrz_feedback
- ? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
+ ? LRZ_FEEDBACK_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
@@ -1208,7 +1208,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
screen->info->a6xx.has_lrz_feedback
- ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z
+ ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
}
@@ -1305,7 +1305,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
.force_lrz_write_dis = !screen->info->a6xx.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = screen->info->a6xx.has_lrz_feedback
- ? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
+ ? LRZ_FEEDBACK_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
@@ -1332,7 +1332,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask =
screen->info->a6xx.has_lrz_feedback
- ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_LRZ_LATE_Z
+ ? LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});
}
@@ -1344,7 +1344,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
.force_lrz_write_dis = !ctx->screen->info->a6xx.has_lrz_feedback,
.buffers_location = BUFFERS_IN_GMEM,
.lrz_feedback_zmode_mask = ctx->screen->info->a6xx.has_lrz_feedback
- ? LRZ_FEEDBACK_EARLY_LRZ_LATE_Z
+ ? LRZ_FEEDBACK_EARLY_Z_LATE_Z
: LRZ_FEEDBACK_NONE,
});