From ddf31d2f407bcb101aeb163bd72b0c4432aea9c4 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Tue, 2 Apr 2024 14:43:27 +0300 Subject: [PATCH] anv: move 3DSTATE_MULTISAMPLE to partial emission Signed-off-by: Lionel Landwerlin Reviewed-by: Ivan Briano Part-of: --- src/intel/vulkan/anv_cmd_buffer.c | 2 +- src/intel/vulkan/anv_pipeline.c | 5 ----- src/intel/vulkan/anv_private.h | 14 +++++++------- src/intel/vulkan/genX_gfx_state.c | 19 ++++++++++++++----- src/intel/vulkan/genX_pipeline.c | 4 +--- 5 files changed, 23 insertions(+), 21 deletions(-) diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c index a877eb291d5..25a79f3e52f 100644 --- a/src/intel/vulkan/anv_cmd_buffer.c +++ b/src/intel/vulkan/anv_cmd_buffer.c @@ -562,7 +562,6 @@ anv_cmd_buffer_flush_pipeline_state(struct anv_cmd_buffer *cmd_buffer, diff_fix_state(PRIMITIVE_REPLICATION, final.primitive_replication); diff_fix_state(SBE, final.sbe); diff_fix_state(SBE_SWIZ, final.sbe_swiz); - diff_fix_state(MULTISAMPLE, final.ms); diff_fix_state(VS, final.vs); diff_fix_state(HS, final.hs); diff_fix_state(DS, final.ds); @@ -570,6 +569,7 @@ anv_cmd_buffer_flush_pipeline_state(struct anv_cmd_buffer *cmd_buffer, diff_fix_state(CLIP, partial.clip); diff_fix_state(SF, partial.sf); diff_fix_state(RASTER, partial.raster); + diff_fix_state(MULTISAMPLE, partial.ms); diff_fix_state(WM, partial.wm); diff_fix_state(STREAMOUT, partial.so); diff_fix_state(GS, partial.gs); diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 807d80a99bc..8739284df83 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -2910,11 +2910,6 @@ anv_graphics_pipeline_emit(struct anv_graphics_pipeline *pipeline, /* TODO(mesh): Mesh vs. Multiview with Instancing. */ } - /* Store line mode and rasterization samples, these are used - * for dynamic primitive topology. - */ - pipeline->rasterization_samples = - state->ms != NULL ? state->ms->rasterization_samples : 1; pipeline->dynamic_patch_control_points = anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_CTRL) && diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 5f18db16e96..8c75ebb069d 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -1416,7 +1416,6 @@ enum anv_gfx_state_bits { ANV_GFX_STATE_VF_SGVS_VI, /* 3DSTATE_VERTEX_ELEMENTS for sgvs elements */ ANV_GFX_STATE_VF_SGVS_INSTANCING, /* 3DSTATE_VF_INSTANCING for sgvs elements */ ANV_GFX_STATE_PRIMITIVE_REPLICATION, - ANV_GFX_STATE_MULTISAMPLE, ANV_GFX_STATE_SBE, ANV_GFX_STATE_SBE_SWIZ, ANV_GFX_STATE_SO_DECL_LIST, @@ -1443,6 +1442,7 @@ enum anv_gfx_state_bits { ANV_GFX_STATE_DEPTH_BOUNDS, ANV_GFX_STATE_INDEX_BUFFER, ANV_GFX_STATE_LINE_STIPPLE, + ANV_GFX_STATE_MULTISAMPLE, ANV_GFX_STATE_PS_BLEND, ANV_GFX_STATE_RASTER, ANV_GFX_STATE_SAMPLE_MASK, @@ -1553,6 +1553,11 @@ struct anv_gfx_dynamic_state { uint32_t LineStippleRepeatCount; } ls; + /* 3DSTATE_MULTISAMPLE */ + struct { + uint32_t NumberofMultisamples; + } ms; + /* 3DSTATE_PS */ struct { uint32_t PositionXYOffsetSelect; @@ -4596,11 +4601,6 @@ struct anv_graphics_pipeline { */ bool dynamic_patch_control_points; - /* This field is required with dynamic primitive topology, - * rasterization_samples used only with gen < 8. - */ - uint32_t rasterization_samples; - uint32_t view_mask; uint32_t instance_multiplier; @@ -4656,7 +4656,6 @@ struct anv_graphics_pipeline { struct anv_gfx_state_ptr sbe; struct anv_gfx_state_ptr sbe_swiz; struct anv_gfx_state_ptr so_decl_list; - struct anv_gfx_state_ptr ms; struct anv_gfx_state_ptr vs; struct anv_gfx_state_ptr hs; struct anv_gfx_state_ptr ds; @@ -4678,6 +4677,7 @@ struct anv_graphics_pipeline { struct anv_gfx_state_ptr clip; struct anv_gfx_state_ptr sf; struct anv_gfx_state_ptr raster; + struct anv_gfx_state_ptr ms; struct anv_gfx_state_ptr ps_extra; struct anv_gfx_state_ptr wm; struct anv_gfx_state_ptr so; diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c index 689cc1cf247..5f0b1e1c538 100644 --- a/src/intel/vulkan/genX_gfx_state.c +++ b/src/intel/vulkan/genX_gfx_state.c @@ -833,7 +833,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) const VkLineRasterizationModeKHR line_mode = anv_line_rasterization_mode(dyn->rs.line.mode, - pipeline->rasterization_samples); + dyn->ms.rasterization_samples); const VkPolygonMode dynamic_raster_mode = genX(raster_polygon_mode)(pipeline, @@ -888,6 +888,11 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT); } + if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES)) { + SET(MULTISAMPLE, ms.NumberofMultisamples, + __builtin_ffs(MAX2(dyn->ms.rasterization_samples, 1)) - 1); + } + if (BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_SAMPLE_MASK)) { /* From the Vulkan 1.0 spec: * If pSampleMask is NULL, it is treated as if the mask has all bits @@ -1185,7 +1190,7 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer) if (instance->intel_enable_wa_14018912822 && intel_needs_workaround(cmd_buffer->device->info, 14018912822) && - pipeline->rasterization_samples > 1) { + dyn->ms.rasterization_samples > 1) { if (DestinationBlendFactor == BLENDFACTOR_ZERO) { DestinationBlendFactor = BLENDFACTOR_CONST_COLOR; color_blend_zero = true; @@ -1601,9 +1606,6 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer) sizeof(struct intel_urb_config)); } - if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE)) - anv_batch_emit_pipeline_state(&cmd_buffer->batch, pipeline, final.ms); - if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION)) anv_batch_emit_pipeline_state(&cmd_buffer->batch, pipeline, final.primitive_replication); @@ -1974,6 +1976,13 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer) } } + if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE)) { + anv_batch_emit_merge(&cmd_buffer->batch, GENX(3DSTATE_MULTISAMPLE), + pipeline, partial.ms, ms) { + SET(ms, ms, NumberofMultisamples); + } + } + if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_CC_STATE)) { hw_state->cc.state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c index c93c99f8b91..f667c8bacbd 100644 --- a/src/intel/vulkan/genX_pipeline.c +++ b/src/intel/vulkan/genX_pipeline.c @@ -848,9 +848,7 @@ static void emit_ms_state(struct anv_graphics_pipeline *pipeline, const struct vk_multisample_state *ms) { - anv_pipeline_emit(pipeline, final.ms, GENX(3DSTATE_MULTISAMPLE), ms) { - ms.NumberofMultisamples = __builtin_ffs(pipeline->rasterization_samples) - 1; - + anv_pipeline_emit(pipeline, partial.ms, GENX(3DSTATE_MULTISAMPLE), ms) { ms.PixelLocation = CENTER; /* The PRM says that this bit is valid only for DX9: