diff --git a/src/intel/vulkan/grl/grl_metakernel_gen.py b/src/intel/vulkan/grl/grl_metakernel_gen.py
index 9e09df8a96d..7861b085c62 100644
--- a/src/intel/vulkan/grl/grl_metakernel_gen.py
+++ b/src/intel/vulkan/grl/grl_metakernel_gen.py
@@ -239,8 +239,13 @@ class Expression(SSAStatement):
 
     def write_c(self, w):
         if self.zone == 'cpu':
-            w.write('uint64_t {} = ', self.c_name)
             c_cpu_vals = [s.c_cpu_val() for s in self.srcs]
+            # There is one bitfield that is a uint64_t, but only holds 2 bits.
+            # In practice we won't overflow, but let's help the compiler (and
+            # coverity) out here.
+            if self.op == '<<':
+                w.write(f'assume({c_cpu_vals[0]} < (1 << 8));')
+            w.write('uint64_t {} = ', self.c_name)
             if len(self.srcs) == 1:
                 w.write('({} {})', self.op, c_cpu_vals[0])
             elif len(self.srcs) == 2: