diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 28ab8109a6e..89a9bb3561a 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -419,6 +419,7 @@ struct ac_surf_config { unsigned is_1d : 1; unsigned is_3d : 1; unsigned is_cube : 1; + unsigned is_array : 1; }; /* Output parameters for ac_surface_compute_nbc_view */ diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c index 75bd8294d2e..6ad96d9f807 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c @@ -91,6 +91,8 @@ radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws, const struct ac_surf_ config.is_1d = type == RADEON_SURF_TYPE_1D || type == RADEON_SURF_TYPE_1D_ARRAY; config.is_3d = type == RADEON_SURF_TYPE_3D; config.is_cube = type == RADEON_SURF_TYPE_CUBEMAP; + config.is_array = type == RADEON_SURF_TYPE_1D_ARRAY || + type == RADEON_SURF_TYPE_2D_ARRAY; return ac_compute_surface(ws->addrlib, &ws->info, &config, mode, surf); } diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c index 100248aa450..62b5b905b2f 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c @@ -93,6 +93,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, tex->target == PIPE_TEXTURE_1D_ARRAY; config.is_3d = tex->target == PIPE_TEXTURE_3D; config.is_cube = tex->target == PIPE_TEXTURE_CUBE; + config.is_array = tex->target == PIPE_TEXTURE_1D_ARRAY || + tex->target == PIPE_TEXTURE_2D_ARRAY || + tex->target == PIPE_TEXTURE_CUBE_ARRAY; /* Use different surface counters for color and FMASK, so that MSAA MRTs * always use consecutive surface indices when FMASK is allocated between diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c index e06a4a4e75f..0bfc26f5e4c 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c @@ -425,6 +425,9 @@ static int radeon_winsys_surface_init(struct radeon_winsys *rws, config.info.array_size = tex->array_size; config.is_3d = !!(tex->target == PIPE_TEXTURE_3D); config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE); + config.is_array = tex->target == PIPE_TEXTURE_1D_ARRAY || + tex->target == PIPE_TEXTURE_2D_ARRAY || + tex->target == PIPE_TEXTURE_CUBE_ARRAY; si_compute_cmask(&ws->info, &config, surf_ws); }