From db6ae41c658170997579a5845d16dc5d4adb994b Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Tue, 2 Jul 2024 11:02:04 -0400 Subject: [PATCH] intel/blorp: Use WA helpers for depth pipecontrol Instead of unconditionally emitting a pipe control on gfx11+, use the workaround helpers for workarounds 1408224581 and 14014097488. Also, add a check for workaround 14016712196, which is also impacted. Reviewed-by: Lionel Landwerlin Part-of: --- src/intel/blorp/blorp_genX_exec_brw.h | 33 +++++++++++++++------------ 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/src/intel/blorp/blorp_genX_exec_brw.h b/src/intel/blorp/blorp_genX_exec_brw.h index 61582501601..8bc4c7c88c8 100644 --- a/src/intel/blorp/blorp_genX_exec_brw.h +++ b/src/intel/blorp/blorp_genX_exec_brw.h @@ -1307,6 +1307,8 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, const struct blorp_params *params) { const struct isl_device *isl_dev = batch->blorp->isl_dev; + const struct intel_device_info *devinfo = + batch->blorp->compiler->brw->devinfo; uint32_t *dw = blorp_emit_dwords(batch, isl_dev->ds.size / 4); if (dw == NULL) @@ -1358,21 +1360,24 @@ blorp_emit_depth_stencil_config(struct blorp_batch *batch, isl_emit_depth_stencil_hiz_s(isl_dev, dw, &info); -#if GFX_VER >= 11 - /* Wa_1408224581 - * - * Workaround: Gfx12LP Astep only An additional pipe control with - * post-sync = store dword operation would be required.( w/a is to - * have an additional pipe control after the stencil state whenever - * the surface state bits of this state is changing). - * - * This also seems sufficient to handle Wa_14014097488. - */ - blorp_emit(batch, GENX(PIPE_CONTROL), pc) { - pc.PostSyncOperation = WriteImmediateData; - pc.Address = blorp_get_workaround_address(batch); + if (intel_needs_workaround(devinfo, 1408224581) || + intel_needs_workaround(devinfo, 14014097488) || + intel_needs_workaround(devinfo, 14016712196)) { + /* Wa_1408224581 + * + * Workaround: Gfx12LP Astep only An additional pipe control with + * post-sync = store dword operation would be required.( w/a is to + * have an additional pipe control after the stencil state whenever + * the surface state bits of this state is changing). + * + * This also seems sufficient to handle Wa_14014097488 and + * Wa_14016712196. + */ + blorp_emit(batch, GENX(PIPE_CONTROL), pc) { + pc.PostSyncOperation = WriteImmediateData; + pc.Address = blorp_get_workaround_address(batch); + } } -#endif } /* Emits the Optimized HiZ sequence specified in the BDW+ PRMs. The