From db2b1e4d76ea607382a13d688d332b74b823622d Mon Sep 17 00:00:00 2001 From: Ian Romanick Date: Sat, 6 Jul 2024 11:49:44 -0700 Subject: [PATCH] brw/nir: Treat load_btd_{global,local}_arg_addr_intel and load_btd_shader_type_intel as convergent No shader-db changes on any Intel platform. No fossil-db changes on Tiger Lake, Ice Lake, or Skylake. fossil-db: Lunar Lake Totals: Instrs: 141808714 -> 141808513 (-0.00%); split: -0.00%, +0.00% Cycle count: 22177889310 -> 22181410192 (+0.02%); split: -0.00%, +0.02% Spill count: 69892 -> 69890 (-0.00%); split: -0.01%, +0.01% Fill count: 128313 -> 128331 (+0.01%) Max live registers: 48052083 -> 48052742 (+0.00%); split: -0.00%, +0.00% Totals from 549 (0.10% of 551446) affected shaders: Instrs: 911251 -> 911050 (-0.02%); split: -0.10%, +0.07% Cycle count: 1244153266 -> 1247674148 (+0.28%); split: -0.04%, +0.32% Spill count: 15849 -> 15847 (-0.01%); split: -0.04%, +0.03% Fill count: 35087 -> 35105 (+0.05%) Max live registers: 68047 -> 68706 (+0.97%); split: -0.25%, +1.22% Meteor Lake Totals: Instrs: 152744298 -> 152741241 (-0.00%); split: -0.00%, +0.00% Cycle count: 17410258529 -> 17405949054 (-0.02%); split: -0.04%, +0.01% Spill count: 78528 -> 78598 (+0.09%); split: -0.01%, +0.09% Fill count: 147893 -> 147978 (+0.06%); split: -0.00%, +0.06% Scratch Memory Size: 3962880 -> 3969024 (+0.16%) Max live registers: 31887206 -> 31887413 (+0.00%); split: -0.00%, +0.00% Totals from 552 (0.09% of 633315) affected shaders: Instrs: 907279 -> 904222 (-0.34%); split: -0.48%, +0.15% Cycle count: 1152358569 -> 1148049094 (-0.37%); split: -0.56%, +0.19% Spill count: 15290 -> 15360 (+0.46%); split: -0.03%, +0.48% Fill count: 35313 -> 35398 (+0.24%); split: -0.02%, +0.26% Scratch Memory Size: 1313792 -> 1319936 (+0.47%) Max live registers: 34218 -> 34425 (+0.60%); split: -0.47%, +1.08% DG2 Totals: Instrs: 152766492 -> 152763061 (-0.00%); split: -0.00%, +0.00% Cycle count: 17406058608 -> 17406396943 (+0.00%); split: -0.02%, +0.02% Spill count: 78626 -> 78624 (-0.00%); split: -0.01%, +0.01% Fill count: 147956 -> 148007 (+0.03%); split: -0.01%, +0.04% Scratch Memory Size: 3962880 -> 3969024 (+0.16%) Max live registers: 31887158 -> 31887365 (+0.00%); split: -0.00%, +0.00% Totals from 552 (0.09% of 633315) affected shaders: Instrs: 908513 -> 905082 (-0.38%); split: -0.47%, +0.09% Cycle count: 1148162185 -> 1148500520 (+0.03%); split: -0.23%, +0.26% Spill count: 15364 -> 15362 (-0.01%); split: -0.07%, +0.06% Fill count: 35343 -> 35394 (+0.14%); split: -0.03%, +0.17% Scratch Memory Size: 1313792 -> 1319936 (+0.47%) Max live registers: 34218 -> 34425 (+0.60%); split: -0.47%, +1.08% Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_fs_nir.cpp | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index d76a8f84b2b..99bf67abd3e 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -1977,6 +1977,9 @@ get_nir_def(nir_to_brw_state &ntb, const nir_def &def, bool all_sources_uniform) nir_instr_as_intrinsic(def.parent_instr); switch (instr->intrinsic) { + case nir_intrinsic_load_btd_global_arg_addr_intel: + case nir_intrinsic_load_btd_local_arg_addr_intel: + case nir_intrinsic_load_btd_shader_type_intel: case nir_intrinsic_load_inline_data_intel: case nir_intrinsic_load_reloc_const_intel: case nir_intrinsic_load_workgroup_id: @@ -4758,17 +4761,19 @@ fs_nir_emit_bs_intrinsic(nir_to_brw_state &ntb, if (nir_intrinsic_infos[instr->intrinsic].has_dest) dest = get_nir_def(ntb, instr->def); + const fs_builder xbld = dest.is_scalar ? bld.scalar_group() : bld; + switch (instr->intrinsic) { case nir_intrinsic_load_btd_global_arg_addr_intel: - bld.MOV(dest, retype(payload.global_arg_ptr, dest.type)); + xbld.MOV(dest, retype(payload.global_arg_ptr, dest.type)); break; case nir_intrinsic_load_btd_local_arg_addr_intel: - bld.MOV(dest, retype(payload.local_arg_ptr, dest.type)); + xbld.MOV(dest, retype(payload.local_arg_ptr, dest.type)); break; case nir_intrinsic_load_btd_shader_type_intel: - payload.load_shader_type(bld, dest); + payload.load_shader_type(xbld, dest); break; default: @@ -5015,19 +5020,11 @@ try_rebuild_source(nir_to_brw_state &ntb, const brw::fs_builder &bld, } case nir_intrinsic_load_btd_local_arg_addr_intel: { - assert(brw_shader_stage_is_bindless(ntb.s.stage)); - const bs_thread_payload &payload = ntb.s.bs_payload(); - ubld.MOV(retype(payload.local_arg_ptr, BRW_TYPE_Q), - &ntb.resource_insts[def->index]); - break; + unreachable("load_btd_local_arg_addr_intel should already be is_scalar"); } case nir_intrinsic_load_btd_global_arg_addr_intel: { - assert(brw_shader_stage_is_bindless(ntb.s.stage)); - const bs_thread_payload &payload = ntb.s.bs_payload(); - ubld.MOV(retype(payload.global_arg_ptr, BRW_TYPE_Q), - &ntb.resource_insts[def->index]); - break; + unreachable("load_btd_global_arg_addr_intel should already be is_scalar"); } case nir_intrinsic_load_reloc_const_intel: {