From daea7e1651dc1d43e645ac3b9d867767257e014d Mon Sep 17 00:00:00 2001
From: Rohan Garg <rohan.garg@intel.com>
Date: Mon, 16 Sep 2024 16:07:03 +0200
Subject: [PATCH] intel/compiler: use the correct cache enum for loads and
 stores

Fixes: 74efde7 ('intel/brw/xehp+: Drop redundant arguments of lsc_msg_desc*()')

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30742>
---
 src/intel/compiler/brw_lower_logical_sends.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp
index f7e810488ed..21d671cdbb4 100644
--- a/src/intel/compiler/brw_lower_logical_sends.cpp
+++ b/src/intel/compiler/brw_lower_logical_sends.cpp
@@ -114,7 +114,7 @@ lower_urb_read_logical_send_xe2(const fs_builder &bld, fs_inst *inst)
                              LSC_ADDR_SURFTYPE_FLAT, LSC_ADDR_SIZE_A32,
                              LSC_DATA_SIZE_D32, dst_comps /* num_channels */,
                              false /* transpose */,
-                             LSC_CACHE(devinfo, STORE, L1UC_L3UC));
+                             LSC_CACHE(devinfo, LOAD, L1UC_L3UC));
 
    /* Update the original instruction. */
    inst->opcode = SHADER_OPCODE_SEND;