From dacc3cc597068d6ac926cd850d45d9b5f711aeca Mon Sep 17 00:00:00 2001 From: Jesse Natalie Date: Tue, 2 May 2023 16:20:28 -0700 Subject: [PATCH] dzn: Use the nir hash as an input to the dxil hash Instead of re-computing all the same bits we already computed, just use the nir hash. Helps prevent missing a bit between the two. Part-of: --- src/microsoft/vulkan/dzn_pipeline.c | 23 +++++------------------ 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/src/microsoft/vulkan/dzn_pipeline.c b/src/microsoft/vulkan/dzn_pipeline.c index b13d1069682..04aea044ec4 100644 --- a/src/microsoft/vulkan/dzn_pipeline.c +++ b/src/microsoft/vulkan/dzn_pipeline.c @@ -737,6 +737,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, const VkPipelineShaderStageCreateInfo *info; uint8_t spirv_hash[SHA1_DIGEST_LENGTH]; uint8_t dxil_hash[SHA1_DIGEST_LENGTH]; + uint8_t nir_hash[SHA1_DIGEST_LENGTH]; uint8_t link_hashes[SHA1_DIGEST_LENGTH][2]; } stages[MESA_VULKAN_SHADER_STAGES] = { 0 }; const uint8_t *dxil_hashes[MESA_VULKAN_SHADER_STAGES] = { 0 }; @@ -849,7 +850,6 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, nir_opts.lower_base_vertex = true; u_foreach_bit(stage, active_stage_mask) { struct mesa_sha1 nir_hash_ctx; - uint8_t nir_hash[SHA1_DIGEST_LENGTH]; const VkPipelineShaderStageRequiredSubgroupSizeCreateInfo *subgroup_size = (const VkPipelineShaderStageRequiredSubgroupSizeCreateInfo *) @@ -873,7 +873,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, } _mesa_sha1_update(&nir_hash_ctx, &subgroup_enum, sizeof(subgroup_enum)); _mesa_sha1_update(&nir_hash_ctx, stages[stage].spirv_hash, sizeof(stages[stage].spirv_hash)); - _mesa_sha1_final(&nir_hash_ctx, nir_hash); + _mesa_sha1_final(&nir_hash_ctx, stages[stage].nir_hash); } struct dzn_nir_options options = { @@ -889,7 +889,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, }; ret = dzn_pipeline_get_nir_shader(device, layout, - cache, nir_hash, + cache, stages[stage].nir_hash, stages[stage].info, stage, &options, &pipeline->templates.shaders[stage].nir); @@ -979,21 +979,7 @@ dzn_graphics_pipeline_compile_shaders(struct dzn_device *device, struct mesa_sha1 dxil_hash_ctx; _mesa_sha1_init(&dxil_hash_ctx); - - if (stage == MESA_SHADER_VERTEX) - _mesa_sha1_update(&dxil_hash_ctx, attribs_hash, sizeof(attribs_hash)); - - if (stage == last_raster_stage) { - _mesa_sha1_update(&dxil_hash_ctx, &yz_flip_mode, sizeof(yz_flip_mode)); - _mesa_sha1_update(&dxil_hash_ctx, &y_flip_mask, sizeof(y_flip_mask)); - _mesa_sha1_update(&dxil_hash_ctx, &z_flip_mask, sizeof(z_flip_mask)); - } - - if (stage == MESA_SHADER_FRAGMENT) { - _mesa_sha1_update(&dxil_hash_ctx, &force_sample_rate_shading, sizeof(force_sample_rate_shading)); - _mesa_sha1_update(&dxil_hash_ctx, &pipeline->use_gs_for_polygon_mode_point, sizeof(pipeline->use_gs_for_polygon_mode_point)); - } - + _mesa_sha1_update(&dxil_hash_ctx, stages[stage].nir_hash, sizeof(stages[stage].nir_hash)); _mesa_sha1_update(&dxil_hash_ctx, stages[stage].spirv_hash, sizeof(stages[stage].spirv_hash)); _mesa_sha1_update(&dxil_hash_ctx, stages[stage].link_hashes[0], sizeof(stages[stage].link_hashes[0])); _mesa_sha1_update(&dxil_hash_ctx, stages[stage].link_hashes[1], sizeof(stages[stage].link_hashes[1])); @@ -2472,6 +2458,7 @@ dzn_compute_pipeline_compile_shader(struct dzn_device *device, struct mesa_sha1 dxil_hash_ctx; _mesa_sha1_init(&dxil_hash_ctx); + _mesa_sha1_update(&dxil_hash_ctx, nir_hash, sizeof(nir_hash)); _mesa_sha1_update(&dxil_hash_ctx, spirv_hash, sizeof(spirv_hash)); _mesa_sha1_update(&dxil_hash_ctx, bindings_hash, sizeof(bindings_hash)); _mesa_sha1_final(&dxil_hash_ctx, dxil_hash);