diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index a628c130d3d..fe1ef58c0a9 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -7379,7 +7379,7 @@ clusters:
00000000 SP_FS_PVT_MEM_ADDR: 0
00000000 SP_FS_PVT_MEM_ADDR_HI: 0
00000000 SP_FS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
- 00000100 SP_BLEND_CNTL: { UNK8 }
+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
00000000 SP_SRGB_CNTL: { 0 }
00000000 SP_FS_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
@@ -7461,7 +7461,7 @@ clusters:
00000000 SP_FS_PVT_MEM_ADDR: 0
00000000 SP_FS_PVT_MEM_ADDR_HI: 0
00000000 SP_FS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
- 00000100 SP_BLEND_CNTL: { UNK8 }
+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
00000000 SP_SRGB_CNTL: { 0 }
00000000 SP_FS_RENDER_COMPONENTS: { RT0 = 0 | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
diff --git a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
index b93543dd9b5..6f09d3a8baf 100644
--- a/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+++ b/src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
@@ -1162,7 +1162,7 @@ t4 write RB_MRT[0].CONTROL (8820)
RB_MRT[0].BLEND_CONTROL: { RGB_SRC_FACTOR = FACTOR_SRC_COLOR | RGB_BLEND_OPCODE = BLEND_DST_PLUS_SRC | RGB_DEST_FACTOR = FACTOR_DST_COLOR | ALPHA_SRC_FACTOR = FACTOR_SRC_COLOR | ALPHA_BLEND_OPCODE = BLEND_DST_PLUS_SRC | ALPHA_DEST_FACTOR = FACTOR_DST_COLOR }
0000000001054784: 0000: 40882002 00000780 08040804
t4 write SP_BLEND_CNTL (a989)
- SP_BLEND_CNTL: { UNK8 }
+ SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
0000000001054790: 0000: 40a98901 00000100
t4 write RB_BLEND_CNTL (8865)
RB_BLEND_CNTL: { ENABLE_BLEND = 0 | INDEPENDENT_BLEND | SAMPLE_MASK = 0xffff }
@@ -1502,7 +1502,7 @@ t7 opcode: CP_DRAW_INDIRECT_MULTI (2a) (12 dwords)
- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ 00000000 SP_FS_OBJ_START_HI: 0
-!+ 00000100 SP_BLEND_CNTL: { UNK8 }
+!+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
+ 00000000 SP_SRGB_CNTL: { 0 }
!+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
!+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
diff --git a/src/freedreno/.gitlab-ci/reference/fd-clouds.log b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
index 67f1b2bcb55..4a3c5dc1c53 100644
--- a/src/freedreno/.gitlab-ci/reference/fd-clouds.log
+++ b/src/freedreno/.gitlab-ci/reference/fd-clouds.log
@@ -5157,7 +5157,7 @@ t4 write RB_DITHER_CNTL (880e)
RB_DITHER_CNTL: { DITHER_MODE_MRT0 = DITHER_ALWAYS | DITHER_MODE_MRT1 = DITHER_ALWAYS | DITHER_MODE_MRT2 = DITHER_ALWAYS | DITHER_MODE_MRT3 = DITHER_ALWAYS | DITHER_MODE_MRT4 = DITHER_ALWAYS | DITHER_MODE_MRT5 = DITHER_ALWAYS | DITHER_MODE_MRT6 = DITHER_ALWAYS | DITHER_MODE_MRT7 = DITHER_ALWAYS }
0000000001124080: 0000: 40880e01 00005555
t4 write SP_BLEND_CNTL (a989)
- SP_BLEND_CNTL: { UNK8 }
+ SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
0000000001124088: 0000: 40a98901 00000100
t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
@@ -6728,7 +6728,7 @@ t7 opcode: CP_DRAW_INDX_OFFSET (38) (4 dwords)
- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
+ 00000000 SP_FS_OBJ_START_HI: 0
-!+ 00000100 SP_BLEND_CNTL: { UNK8 }
+!+ 00000100 SP_BLEND_CNTL: { ENABLE_BLEND = 0 | UNK8 }
+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
!+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 }
!+ 00000004 SP_FS_OUTPUT[0].REG: { REGID = r1.x }
diff --git a/src/freedreno/registers/adreno/a5xx.xml b/src/freedreno/registers/adreno/a5xx.xml
index b340ee7b017..5b544859874 100644
--- a/src/freedreno/registers/adreno/a5xx.xml
+++ b/src/freedreno/registers/adreno/a5xx.xml
@@ -2527,7 +2527,8 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set
-
+
+
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_blend.c b/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
index f9ad66aca64..84ef81a8153 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_blend.c
@@ -126,9 +126,9 @@ fd5_blend_state_create(struct pipe_context *pctx,
COND(cso->alpha_to_coverage, A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE) |
COND(cso->independent_blend_enable, A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND);
so->sp_blend_cntl =
+ A5XX_SP_BLEND_CNTL_ENABLE_BLEND(mrt_blend) |
A5XX_SP_BLEND_CNTL_UNK8 |
- COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE) |
- COND(mrt_blend, A5XX_SP_BLEND_CNTL_ENABLED);
+ COND(cso->alpha_to_coverage, A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE);
return so;
}