From d9f1f0e9b90deee872bc93f1d96f97a741286461 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 17 Dec 2025 13:33:27 -0800 Subject: [PATCH] tu: Drop use of legacy reg offset macros Signed-off-by: Rob Clark Part-of: --- src/freedreno/vulkan/tu_clear_blit.cc | 10 +++++----- src/freedreno/vulkan/tu_cmd_buffer.cc | 14 +++++++------- src/freedreno/vulkan/tu_lrz.cc | 4 ++-- src/freedreno/vulkan/tu_query_pool.cc | 9 ++++++--- 4 files changed, 20 insertions(+), 17 deletions(-) diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc index 4b02ac24982..074507da370 100644 --- a/src/freedreno/vulkan/tu_clear_blit.cc +++ b/src/freedreno/vulkan/tu_clear_blit.cc @@ -5311,12 +5311,12 @@ store_3d_blit(struct tu_cmd_buffer *cmd, * save/restore them dynamically. */ tu_cs_emit_pkt7(cs, CP_REG_TO_SCRATCH, 1); - tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(REG_A6XX_RB_CNTL) | + tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(RB_CNTL(CHIP).reg) | CP_REG_TO_SCRATCH_0_SCRATCH(0) | CP_REG_TO_SCRATCH_0_CNT(1 - 1)); if (CHIP >= A7XX) { tu_cs_emit_pkt7(cs, CP_REG_TO_SCRATCH, 1); - tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(REG_A7XX_RB_BUFFER_CNTL) | + tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(RB_BUFFER_CNTL(CHIP).reg) | CP_REG_TO_SCRATCH_0_SCRATCH(1) | CP_REG_TO_SCRATCH_0_CNT(1 - 1)); } @@ -5357,18 +5357,18 @@ store_3d_blit(struct tu_cmd_buffer *cmd, /* Restore RB_CNTL/GRAS_SC_BIN_CNTL saved above. */ tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1); - tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_RB_CNTL) | + tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(RB_CNTL(CHIP).reg) | CP_SCRATCH_TO_REG_0_SCRATCH(0) | CP_SCRATCH_TO_REG_0_CNT(1 - 1)); tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1); - tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_GRAS_SC_BIN_CNTL) | + tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(GRAS_SC_BIN_CNTL(CHIP).reg) | CP_SCRATCH_TO_REG_0_SCRATCH(0) | CP_SCRATCH_TO_REG_0_CNT(1 - 1)); if (CHIP >= A7XX) { tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1); - tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A7XX_RB_BUFFER_CNTL) | + tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(RB_BUFFER_CNTL(CHIP).reg) | CP_SCRATCH_TO_REG_0_SCRATCH(1) | CP_SCRATCH_TO_REG_0_CNT(1 - 1)); } diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 08a40266ec0..2032c0b99ad 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -926,7 +926,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd, } if (no_track) { - tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CNTL, 1); + tu_cs_emit_pkt4(cs, RB_RENDER_CNTL(A6XX).reg, 1); tu_cs_emit(cs, cntl); return; } @@ -945,7 +945,7 @@ tu6_emit_render_cntl(struct tu_cmd_buffer *cmd, tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3); tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL)); - tu_cs_emit(cs, REG_A6XX_RB_RENDER_CNTL); + tu_cs_emit(cs, RB_RENDER_CNTL(A6XX).reg); tu_cs_emit(cs, cntl); } @@ -9124,7 +9124,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd, * previous dispatches to finish. */ tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3); - tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A7XX_SP_CS_NDRANGE_1)); + tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(SP_CS_NDRANGE_1(CHIP).reg)); tu_cs_emit_qw(cs, info->indirect); tu_cs_emit_pkt7(cs, CP_SCRATCH_WRITE, 2); @@ -9149,7 +9149,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd, CP_REG_RMW_0_SKIP_WAIT_FOR_ME | CP_REG_RMW_0_SRC0_IS_REG | CP_REG_RMW_0_SRC1_ADD); - tu_cs_emit(cs, REG_A7XX_SP_CS_NDRANGE_1); /* SRC0 */ + tu_cs_emit(cs, SP_CS_NDRANGE_1(CHIP).reg); /* SRC0 */ tu_cs_emit(cs, -1); /* SRC1 */ /* scratch0 = ((scratch0 & (local_size - 1)) rot 2 @@ -9167,7 +9167,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd, /* write scratch0 to SP_CS_NDRANGE_7 */ tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1); tu_cs_emit(cs, - CP_SCRATCH_TO_REG_0_REG(REG_A7XX_SP_CS_NDRANGE_7) | + CP_SCRATCH_TO_REG_0_REG(SP_CS_NDRANGE_7(CHIP).reg) | CP_SCRATCH_TO_REG_0_SCRATCH(0)); tu_cs_emit_pkt7(cs, CP_SCRATCH_WRITE, 2); @@ -9185,7 +9185,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd, CP_REG_RMW_0_SKIP_WAIT_FOR_ME | CP_REG_RMW_0_SRC0_IS_REG | CP_REG_RMW_0_SRC1_ADD); - tu_cs_emit(cs, REG_A7XX_SP_CS_NDRANGE_1); /* SRC0 */ + tu_cs_emit(cs, SP_CS_NDRANGE_1(CHIP).reg); /* SRC0 */ tu_cs_emit(cs, local_size[0] - 1); /* SRC1 */ unsigned local_size_log2 = util_logbase2(local_size[0]); @@ -9207,7 +9207,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd, /* write scratch0 to SP_CS_KERNEL_GROUP_X */ tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1); tu_cs_emit(cs, - CP_SCRATCH_TO_REG_0_REG(REG_A7XX_SP_CS_KERNEL_GROUP_X) | + CP_SCRATCH_TO_REG_0_REG(SP_CS_KERNEL_GROUP_X(CHIP).reg) | CP_SCRATCH_TO_REG_0_SCRATCH(0)); } else { tu_cs_emit_regs(cs, diff --git a/src/freedreno/vulkan/tu_lrz.cc b/src/freedreno/vulkan/tu_lrz.cc index 0402378a25e..e36f7a23cd3 100644 --- a/src/freedreno/vulkan/tu_lrz.cc +++ b/src/freedreno/vulkan/tu_lrz.cc @@ -732,14 +732,14 @@ tu_lrz_before_sysmem_br(struct tu_cmd_buffer *cmd, struct tu_cs *cs) tu_cs_emit(cs, if_dwords + 1); /* GRAS_LRZ_DEPTH_CLEAR = lrz_fc->buffer[1].depth_clear_val */ tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3); - tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A7XX_GRAS_LRZ_DEPTH_CLEAR)); + tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(GRAS_LRZ_DEPTH_CLEAR(CHIP).reg)); tu_cs_emit_qw(cs, lrz_fc_iova + offsetof(fd_lrzfc_layout, buffer[1].depth_clear_val)); /* } else { */ tu_cs_emit_pkt7(cs, CP_NOP, else_dwords); /* GRAS_LRZ_DEPTH_CLEAR = lrz_fc->buffer[0].depth_clear_val */ tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3); - tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A7XX_GRAS_LRZ_DEPTH_CLEAR)); + tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(GRAS_LRZ_DEPTH_CLEAR(CHIP).reg)); tu_cs_emit_qw(cs, lrz_fc_iova + offsetof(fd_lrzfc_layout, buffer[0].depth_clear_val)); /* } */ diff --git a/src/freedreno/vulkan/tu_query_pool.cc b/src/freedreno/vulkan/tu_query_pool.cc index 98ca316f0ba..a3b2dabd0b7 100644 --- a/src/freedreno/vulkan/tu_query_pool.cc +++ b/src/freedreno/vulkan/tu_query_pool.cc @@ -28,6 +28,7 @@ #define NSEC_PER_SEC 1000000000ull #define WAIT_TIMEOUT 5 #define STAT_COUNT ((REG_A6XX_RBBM_PIPESTAT_CSINVOCATIONS - REG_A6XX_RBBM_PIPESTAT_IAVERTICES) / 2 + 1) +#define COUNTER_REG(name) __RBBM_PIPESTAT_ ## name ({}).reg struct PACKED query_slot { uint64_t available; @@ -1365,7 +1366,7 @@ emit_begin_prim_generated_query(struct tu_cmd_buffer *cmdbuf, tu_cs_emit_wfi(cs); tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); - tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PIPESTAT_CINVOCATIONS) | + tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(COUNTER_REG(CINVOCATIONS)) | CP_REG_TO_MEM_0_CNT(2) | CP_REG_TO_MEM_0_64B); tu_cs_emit_qw(cs, begin_iova); @@ -1918,7 +1919,7 @@ emit_end_prim_generated_query(struct tu_cmd_buffer *cmdbuf, tu_cs_emit_wfi(cs); tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); - tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PIPESTAT_CINVOCATIONS) | + tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(COUNTER_REG(CINVOCATIONS)) | CP_REG_TO_MEM_0_CNT(2) | CP_REG_TO_MEM_0_64B); tu_cs_emit_qw(cs, end_iova); @@ -2031,6 +2032,7 @@ tu_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, } TU_GENX(tu_CmdEndQueryIndexedEXT); +template VKAPI_ATTR void VKAPI_CALL tu_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits2 pipelineStage, @@ -2067,7 +2069,7 @@ tu_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, } tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3); - tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_ALWAYS_ON_COUNTER) | + tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(__CP_ALWAYS_ON_COUNTER({}).reg) | CP_REG_TO_MEM_0_CNT(2) | CP_REG_TO_MEM_0_64B); tu_cs_emit_qw(cs, query_result_iova(pool, query, uint64_t, 0)); @@ -2108,6 +2110,7 @@ tu_CmdWriteTimestamp2(VkCommandBuffer commandBuffer, */ handle_multiview_queries(cmd, pool, query); } +TU_GENX(tu_CmdWriteTimestamp2); VKAPI_ATTR void VKAPI_CALL tu_CmdWriteAccelerationStructuresPropertiesKHR(VkCommandBuffer commandBuffer,