diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 05135d16427..197153c8231 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -1744,6 +1744,11 @@ struct anv_gfx_dynamic_state {
 
    bool pma_fix;
 
+   /**
+    * DEPTH and STENCIL attachment write state for Wa_18019816803.
+    */
+   bool ds_write_state;
+
    BITSET_DECLARE(dirty, ANV_GFX_STATE_MAX);
 };
 
@@ -3731,11 +3736,6 @@ struct anv_cmd_graphics_state {
    bool color_blend_zero;
    bool alpha_blend_zero;
 
-   /**
-    * DEPTH and STENCIL attachment write state for Wa_18019816803.
-    */
-   bool ds_write_state;
-
    /**
     * State tracking for Wa_18020335297.
     */
diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index c62eff8a7bf..fa0a6f9c18d 100644
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -317,15 +317,15 @@ blorp_exec_on_render(struct blorp_batch *batch,
    }
 #endif
 
-#if GFX_VERx10 >= 125
+#if INTEL_WA_18019816803_GFX_VER
    /* Check if blorp ds state matches ours. */
    if (intel_needs_workaround(cmd_buffer->device->info, 18019816803)) {
       bool blorp_ds_state = params->depth.enabled || params->stencil.enabled;
-      if (cmd_buffer->state.gfx.ds_write_state != blorp_ds_state) {
+      if (hw_state->ds_write_state != blorp_ds_state) {
          /* Flag the change in ds_write_state so that the next pipeline use
           * will trigger a PIPE_CONTROL too.
           */
-         cmd_buffer->state.gfx.ds_write_state = blorp_ds_state;
+         hw_state->ds_write_state = blorp_ds_state;
          BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WA_18019816803);
 
          /* Add the stall that will flush prior to the blorp operation by
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index e8dae143e61..cd014ca7c26 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3371,7 +3371,6 @@ genX(CmdExecuteCommands)(
    container->state.current_l3_config = NULL;
    container->state.current_hash_scale = 0;
    container->state.gfx.push_constant_stages = 0;
-   container->state.gfx.ds_write_state = false;
 
    memset(&container->state.gfx.urb_cfg, 0, sizeof(struct intel_urb_config));
 
diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c
index 504dc8aaae0..b07384ad04e 100644
--- a/src/intel/vulkan/genX_gfx_state.c
+++ b/src/intel/vulkan/genX_gfx_state.c
@@ -968,13 +968,10 @@ genX(cmd_buffer_flush_gfx_runtime_state)(struct anv_cmd_buffer *cmd_buffer)
       SET(PMA_FIX, pma_fix, pma);
 #endif
 
-#if GFX_VERx10 >= 125
+#if INTEL_WA_18019816803_GFX_VER
       if (intel_needs_workaround(cmd_buffer->device->info, 18019816803)) {
          bool ds_write_state = opt_ds.depth.write_enable || opt_ds.stencil.write_enable;
-         if (gfx->ds_write_state != ds_write_state) {
-            gfx->ds_write_state = ds_write_state;
-            BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WA_18019816803);
-         }
+         SET(WA_18019816803, ds_write_state, ds_write_state);
       }
 #endif
    }
@@ -2192,7 +2189,7 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
       }
    }
 
-#if GFX_VERx10 >= 125
+#if INTEL_WA_18019816803_GFX_VER
    if (BITSET_TEST(hw_state->dirty, ANV_GFX_STATE_WA_18019816803)) {
       genx_batch_emit_pipe_control(&cmd_buffer->batch, cmd_buffer->device->info,
                                    cmd_buffer->state.current_pipeline,