From d95e90ab5ffa228ce732f860b0b4c13726d1447a Mon Sep 17 00:00:00 2001 From: Georg Lehmann Date: Sat, 7 Jun 2025 13:13:11 +0200 Subject: [PATCH] aco: do not use v_cvt_pk_u8_f32 for f2u8 The ISA docs don't mention this, but instead of always truncating like other integer conversions, this opcode actually uses the single precision rounding mode. We could continue to use the opcode and set the rounding mode to rtz in lower_to_hw_instrs, but I think I should just concede that f2u8 isn't worth the effort. Fixes: 9bb10b58 ("aco: use v_cvt_pk_u8_f32 for f2u8") Reviewed-by: Rhys Perry Part-of: --- .../compiler/instruction_selection/aco_select_nir_alu.cpp | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp b/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp index ce20d2fd724..37302231cdd 100644 --- a/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp +++ b/src/amd/compiler/instruction_selection/aco_select_nir_alu.cpp @@ -2733,11 +2733,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) } } } else if (instr->src[0].src.ssa->bit_size == 32) { - if (dst.regClass() == v1b && ctx->program->gfx_level >= GFX11) - bld.vop3(aco_opcode::p_v_cvt_pk_u8_f32, Definition(dst), - get_alu_src(ctx, instr->src[0])); - else - emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f32, dst); + emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f32, dst); } else { emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_u32_f64, dst); }