From d8ed4f14e6f7836b34a3d17ebfdf344ff5ed4f25 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 14 May 2025 15:07:37 -0700 Subject: [PATCH] freedreno/ir3: Fix tess/geom asan error Fixes: ee0ee2a31747 ("ir3: don't sync every TCS/GEOM block") Signed-off-by: Rob Clark Part-of: --- src/freedreno/ci/freedreno-a630-fails.txt | 4 ---- src/freedreno/ir3/ir3_compiler_nir.c | 8 +++++--- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/freedreno/ci/freedreno-a630-fails.txt b/src/freedreno/ci/freedreno-a630-fails.txt index 817ef61efd6..bb5a091e3d4 100644 --- a/src/freedreno/ci/freedreno-a630-fails.txt +++ b/src/freedreno/ci/freedreno-a630-fails.txt @@ -240,10 +240,6 @@ KHR-GL46.texture_lod_basic.lod_selection,Fail KHR-GL46.texture_lod_bias.texture_lod_bias_all,Fail # a630-gles-asan -asan-dEQP-GLES31.functional.debug.negative_coverage.callbacks.tessellation.invalid_primitive_mode,Crash -asan-dEQP-GLES31.functional.debug.negative_coverage.get_error.tessellation.invalid_primitive_mode,Crash -asan-dEQP-GLES31.functional.debug.negative_coverage.log.tessellation.invalid_primitive_mode,Crash -asan-dEQP-GLES31.functional.state_query.program.tesselation_shader_state_get_programiv,Crash asan-dEQP-GLES31.functional.texture.border_clamp.range_clamp.linear_float_color,Fail # GL tests above, Vulkan tests below diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 72720f77ac0..fe1cb7462cd 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -5887,9 +5887,11 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, */ if (so->type == MESA_SHADER_TESS_CTRL || so->type == MESA_SHADER_GEOMETRY) { struct ir3_block *first_block = ir3_start_block(ir); - struct ir3_instruction *first_instr = list_first_entry( - &first_block->instr_list, struct ir3_instruction, node); - first_instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY; + if (!list_is_empty(&first_block->instr_list)) { + struct ir3_instruction *first_instr = list_first_entry( + &first_block->instr_list, struct ir3_instruction, node); + first_instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY; + } } if (ctx->compiler->gen >= 7 && so->type == MESA_SHADER_COMPUTE) {