From d8bac1002c7d31681f722f1767faf195edf0a51e Mon Sep 17 00:00:00 2001 From: Jesse Natalie Date: Fri, 30 Apr 2021 11:47:15 -0700 Subject: [PATCH] vtn: Use relaxed 24bit opcodes for CL 24bit math Reviewed-by: Jason Ekstrand Reviewed-by: Karol Herbst Part-of: --- src/compiler/spirv/vtn_opencl.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_opencl.c b/src/compiler/spirv/vtn_opencl.c index 2b01e744e27..e07669c53ec 100644 --- a/src/compiler/spirv/vtn_opencl.c +++ b/src/compiler/spirv/vtn_opencl.c @@ -495,13 +495,13 @@ handle_special(struct vtn_builder *b, uint32_t opcode, case OpenCLstd_UMad_hi: return nir_umad_hi(nb, srcs[0], srcs[1], srcs[2]); case OpenCLstd_SMul24: - return nir_imul24(nb, srcs[0], srcs[1]); + return nir_imul24_relaxed(nb, srcs[0], srcs[1]); case OpenCLstd_UMul24: - return nir_umul24(nb, srcs[0], srcs[1]); + return nir_umul24_relaxed(nb, srcs[0], srcs[1]); case OpenCLstd_SMad24: - return nir_imad24(nb, srcs[0], srcs[1], srcs[2]); + return nir_iadd(nb, nir_imul24_relaxed(nb, srcs[0], srcs[1]), srcs[2]); case OpenCLstd_UMad24: - return nir_umad24(nb, srcs[0], srcs[1], srcs[2]); + return nir_umad24_relaxed(nb, srcs[0], srcs[1], srcs[2]); case OpenCLstd_FClamp: return nir_fclamp(nb, srcs[0], srcs[1], srcs[2]); case OpenCLstd_SClamp: