diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index f0270568d11..092b06040b8 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -889,6 +889,20 @@ radv_image_alloc_values(const struct radv_device *device, struct radv_image *ima
       image->tc_compat_zrange_offset = image->size;
       image->size += image->vk.mip_levels * 4;
    }
+
+   if (pdev->info.gfx_level == GFX12) {
+      const struct radeon_surf *surf = &image->planes[0].surface;
+
+      /* All production chips don't support HiS. */
+      assert(!surf->u.gfx9.zs.his.offset);
+
+      /* Allocate HiZ metadata when the image has depth/stencil aspects to implement a workaround. */
+      if (!pdev->use_gfx12_hiz_his_event_wa && surf->u.gfx9.zs.hiz.offset &&
+          (image->vk.aspects == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT))) {
+         image->hiz_valid_offset = image->size;
+         image->size += image->vk.mip_levels * 4;
+      }
+   }
 }
 
 /* Determine if the image is affected by the pipe misaligned metadata issue
diff --git a/src/amd/vulkan/radv_image.h b/src/amd/vulkan/radv_image.h
index c9fad54b599..cb372ab1d7c 100644
--- a/src/amd/vulkan/radv_image.h
+++ b/src/amd/vulkan/radv_image.h
@@ -64,6 +64,11 @@ struct radv_image {
     */
    uint64_t tc_compat_zrange_offset;
 
+   /* Metadata for the HiZ workaround on GFX12 with both depth and stencil planes. It's used to
+    * track whether HiZ metadata are in-sync with main image data, per-level.
+    */
+   uint64_t hiz_valid_offset;
+
    /* For VK_ANDROID_native_buffer, the WSI image owns the memory, */
    VkDeviceMemory owned_memory;