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winsys/amdgpu: Add support for queue priority in Mesa

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This patch adds support for queue priority levels in Mesa's AMDGPU winsys layer.
The changes include:

1. Updated ac_drm_create_userqueue() to accept and pass through flags parameter
2. Modified amdgpu_userq_init() to use the flags when creating queues
3. Added flags field to amdgpu_userq struct to store priority settings
4. Updated header definitions to match kernel UAPI changes

This aligns with the kernel changes provided by Alex:
https://lists.freedesktop.org/archives/amd-gfx/2025-April/122782.html
https://lists.freedesktop.org/archives/amd-gfx/2025-April/122780.html
https://lists.freedesktop.org/archives/amd-gfx/2025-April/122786.html

v2: We only need 1 normal priority queue and 1 TMZ normal priority queue.(Marek Olšák)
v3: Simplified to only support normal priority queues
v4: use a local variable instead of being in struct amdgpu_userq.(Marek Olšák)
v5: rebase the latest main branch.

Signed-off-by: Jesse.Zhang <Jesse.zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34568>
This commit is contained in:
Jesse.Zhang
2025-05-06 10:19:04 +08:00
committed by Marge Bot
parent 870d17012a
commit d8624e6a79
5 changed files with 18 additions and 5 deletions
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9
include/drm-uapi/amdgpu_drm.h
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@@ -329,6 +329,13 @@ union drm_amdgpu_ctx {
#define AMDGPU_USERQ_OP_CREATE 1
#define AMDGPU_USERQ_OP_FREE 2
/* queue priority levels */
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0
/* for queues that need access to protected content */
#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)
/*
* This structure is a container to pass input configuration
* info for all supported userqueue related operations.
@@ -355,7 +362,7 @@ struct drm_amdgpu_userq_in {
* and doorbell_offset in the doorbell bo.
*/
__u32 doorbell_offset;
__u32 _pad;
__u32 flags;
/**
* @queue_va: Virtual address of the GPU memory which holds the queue
* object. The queue holds the workload packets.