From d81809618f08e8d20ccd6a317078b5e0a08443a0 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 14 Mar 2024 08:22:39 +0100 Subject: [PATCH] radv: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT on GFX11 Ported from RadeonSI 7d3a414662ed4aaffd80762532a1c3c9f4cfc4f1 ("radeonsi/gfx11: fix programming of PA_SC_BINNER_CNTL_1.MAX_ALLOC_COUNT") Fixes: 25a66477d02 ("radeonsi/gfx11: register changes") Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/si_cmd_buffer.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 9f405e14b0f..cdd64e09f63 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -514,9 +514,14 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) } if (physical_device->rad_info.gfx_level >= GFX9) { + unsigned max_alloc_count = physical_device->rad_info.pbb_max_alloc_count; + + /* GFX11+ shouldn't subtract 1 from pbb_max_alloc_count. */ + if (physical_device->rad_info.gfx_level < GFX11) + max_alloc_count -= 1; + radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1, - S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) | - S_028C48_MAX_PRIM_PER_BATCH(1023)); + S_028C48_MAX_ALLOC_COUNT(max_alloc_count) | S_028C48_MAX_PRIM_PER_BATCH(1023)); radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1)); radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0); }