From d7d330754b260edb478a9ec76bd2a82a288f6aab Mon Sep 17 00:00:00 2001
From: Daniel Almeida <daniel.almeida@collabora.com>
Date: Mon, 24 Jul 2023 18:56:55 -0300
Subject: [PATCH] nak: add support for nir_op_unpack_half_2x16_split_{x|y}

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
---
 src/nouveau/compiler/nak_encode_sm75.rs |  5 +++++
 src/nouveau/compiler/nak_from_nir.rs    | 21 +++++++++++++++++++++
 src/nouveau/compiler/nak_ir.rs          |  2 ++
 3 files changed, 28 insertions(+)

diff --git a/src/nouveau/compiler/nak_encode_sm75.rs b/src/nouveau/compiler/nak_encode_sm75.rs
index 56d35b9c193..2bdeda6d9a2 100644
--- a/src/nouveau/compiler/nak_encode_sm75.rs
+++ b/src/nouveau/compiler/nak_encode_sm75.rs
@@ -717,6 +717,11 @@ impl SM75Instr {
             ALUSrc::from_src(&op.src.into()),
             ALUSrc::None,
         );
+
+        if op.high {
+            self.set_field(60..62, 1_u8); // .H1
+        }
+
         self.set_field(75..77, (op.dst_type.bits() / 8).ilog2());
         self.set_rnd_mode(78..80, op.rnd_mode);
         self.set_bit(80, op.ftz);
diff --git a/src/nouveau/compiler/nak_from_nir.rs b/src/nouveau/compiler/nak_from_nir.rs
index 7444ec14b19..300311059bb 100644
--- a/src/nouveau/compiler/nak_from_nir.rs
+++ b/src/nouveau/compiler/nak_from_nir.rs
@@ -368,6 +368,7 @@ impl<'a> ShaderFromNir<'a> {
                     dst_type: FloatType::F16,
                     rnd_mode: FRndMode::NearestEven,
                     ftz: true,
+                    high: false,
                 });
                 assert!(alu.def.bit_size() == 32);
                 let dst = b.alloc_ssa(RegFile::GPR, 1);
@@ -378,6 +379,7 @@ impl<'a> ShaderFromNir<'a> {
                     dst_type: FloatType::F32,
                     rnd_mode: FRndMode::NearestEven,
                     ftz: true,
+                    high: false,
                 });
                 dst
             }
@@ -677,6 +679,7 @@ impl<'a> ShaderFromNir<'a> {
                     dst_type: FloatType::F16,
                     rnd_mode: FRndMode::NearestEven,
                     ftz: false,
+                    high: false,
                 });
 
                 let src_bits = usize::from(alu.get_src(1).bit_size());
@@ -689,6 +692,7 @@ impl<'a> ShaderFromNir<'a> {
                     dst_type: FloatType::F16,
                     rnd_mode: FRndMode::NearestEven,
                     ftz: false,
+                    high: false,
                 });
 
                 let dst = b.alloc_ssa(RegFile::GPR, 1);
@@ -742,6 +746,23 @@ impl<'a> ShaderFromNir<'a> {
                 let src0_y = srcs[0].as_ssa().unwrap()[1];
                 b.mov(src0_y.into())
             }
+            nir_op_unpack_half_2x16_split_x
+            | nir_op_unpack_half_2x16_split_y => {
+                assert!(alu.def.bit_size() == 32);
+                let dst = b.alloc_ssa(RegFile::GPR, 1);
+
+                b.push_op(OpF2F {
+                    dst: dst[0].into(),
+                    src: srcs[0],
+                    src_type: FloatType::F16,
+                    dst_type: FloatType::F32,
+                    rnd_mode: FRndMode::NearestEven,
+                    ftz: false,
+                    high: alu.op == nir_op_unpack_half_2x16_split_y,
+                });
+
+                dst
+            }
             nir_op_ushr => {
                 assert!(alu.def.bit_size() == 32);
                 let dst = b.alloc_ssa(RegFile::GPR, 1);
diff --git a/src/nouveau/compiler/nak_ir.rs b/src/nouveau/compiler/nak_ir.rs
index acc16f67f28..80b276b2399 100644
--- a/src/nouveau/compiler/nak_ir.rs
+++ b/src/nouveau/compiler/nak_ir.rs
@@ -2100,6 +2100,8 @@ pub struct OpF2F {
     pub dst_type: FloatType,
     pub rnd_mode: FRndMode,
     pub ftz: bool,
+    /// Place the result into the upper 16 bits of the destination register
+    pub high: bool,
 }
 
 impl fmt::Display for OpF2F {