intel/brw: Introduce new MEMORY_*_LOGICAL opcodes

This is a new unified set of opcodes for memory access loosely patterned
after the new LSC-style data port messages introduced on Alchemist GPUs.

Rather than creating an opcode for every type of memory access, it has
only three opcodes: load, store, and atomic.  It has various sources to
indicate the rest:

- Binding type (raw pointer, pointer to surface state, or BT index)
- Address size (A64, A32, A16)
- Data size (bit size, number of components)
- Opcode (atomic opcode, or LOAD/STORE vs. LOAD_CMASK/STORE_CMASK)
- Mode (typed vs. untyped vs. shared-local vs. scratch)
- Address (and its dimensionality)
- Data (0 for loads, 1 for stores, 2 for atomics)
- Whether we want block access

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>

src/intel/compiler/brw_fs_lower_simd_width.cpp

@@ -377,6 +377,24 @@ brw_fs_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst)
    case SHADER_OPCODE_TXS_LOGICAL:
       return get_sampler_lowered_simd_width(devinfo, inst);
 
+   case SHADER_OPCODE_MEMORY_LOAD_LOGICAL:
+   case SHADER_OPCODE_MEMORY_STORE_LOGICAL:
+   case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL:
+      if (devinfo->ver >= 20)
+         return inst->exec_size;
+
+      if (inst->src[MEMORY_LOGICAL_MODE].ud == MEMORY_MODE_TYPED)
+         return 8;
+
+      /* HDC A64 atomics are limited to SIMD8 */
+      if (!devinfo->has_lsc &&
+          inst->src[MEMORY_LOGICAL_BINDING_TYPE].ud == LSC_ADDR_SURFTYPE_FLAT
+          && lsc_opcode_is_atomic((enum lsc_opcode)
+                                  inst->src[MEMORY_LOGICAL_OPCODE].ud))
+         return 8;
+
+      return MIN2(16, inst->exec_size);
+
    /* On gfx12 parameters are fixed to 16-bit values and therefore they all
     * always fit regardless of the execution size.
     */