diff --git a/src/amd/vulkan/radv_pipeline_rt.c b/src/amd/vulkan/radv_pipeline_rt.c
index 4205fe67dfa..a4468be5382 100644
--- a/src/amd/vulkan/radv_pipeline_rt.c
+++ b/src/amd/vulkan/radv_pipeline_rt.c
@@ -647,6 +647,12 @@ lower_rt_instructions(nir_shader *shader, struct rt_variables *vars, unsigned ca
                nir_ssa_def_rewrite_uses(&intr->dest.ssa, ret);
                break;
             }
+            case nir_intrinsic_load_cull_mask: {
+               b_shader.cursor = nir_instr_remove(instr);
+               nir_ssa_def *ret = nir_load_var(&b_shader, vars->cull_mask);
+               nir_ssa_def_rewrite_uses(&intr->dest.ssa, ret);
+               break;
+            }
             case nir_intrinsic_ignore_ray_intersection: {
                b_shader.cursor = nir_instr_remove(instr);
                nir_store_var(&b_shader, vars->ahit_status, nir_imm_int(&b_shader, 1), 1);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index f7e5470aec7..a0233ef4df7 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -666,6 +666,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_pipeline_
                .multiview = true,
                .physical_storage_buffer_address = true,
                .post_depth_coverage = true,
+               .ray_cull_mask = true,
                .ray_query = true,
                .ray_tracing = true,
                .ray_traversal_primitive_culling = true,