From d59bd421a27996b1ca711aa727e7d6af59bcc0cb Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Sat, 7 Dec 2024 00:23:07 -0800 Subject: [PATCH] intel/brw: Rename fs_inst to brw_inst Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_builder.cpp | 8 +- src/intel/compiler/brw_builder.h | 120 +++++++++--------- src/intel/compiler/brw_cfg.cpp | 10 +- src/intel/compiler/brw_cfg.h | 56 ++++---- src/intel/compiler/brw_compile_fs.cpp | 14 +- src/intel/compiler/brw_compile_gs.cpp | 4 +- src/intel/compiler/brw_compile_mesh.cpp | 2 +- src/intel/compiler/brw_compile_tcs.cpp | 4 +- src/intel/compiler/brw_compile_tes.cpp | 2 +- src/intel/compiler/brw_compile_vs.cpp | 2 +- src/intel/compiler/brw_def_analysis.cpp | 16 +-- src/intel/compiler/brw_disasm_info.cpp | 2 +- src/intel/compiler/brw_disasm_info.h | 4 +- src/intel/compiler/brw_fs.cpp | 28 ++-- src/intel/compiler/brw_fs.h | 24 ++-- src/intel/compiler/brw_fs_live_variables.cpp | 6 +- src/intel/compiler/brw_fs_live_variables.h | 2 +- src/intel/compiler/brw_fs_nir.cpp | 86 ++++++------- src/intel/compiler/brw_fs_visitor.cpp | 8 +- src/intel/compiler/brw_generator.cpp | 20 +-- src/intel/compiler/brw_generator.h | 18 +-- src/intel/compiler/brw_inst.cpp | 86 ++++++------- src/intel/compiler/brw_inst.h | 76 +++++------ src/intel/compiler/brw_ir_performance.cpp | 8 +- src/intel/compiler/brw_lower.cpp | 42 +++--- src/intel/compiler/brw_lower_dpas.cpp | 8 +- .../brw_lower_integer_multiplication.cpp | 12 +- .../compiler/brw_lower_logical_sends.cpp | 56 ++++---- src/intel/compiler/brw_lower_pack.cpp | 2 +- src/intel/compiler/brw_lower_regioning.cpp | 58 ++++----- src/intel/compiler/brw_lower_scoreboard.cpp | 28 ++-- src/intel/compiler/brw_lower_simd_width.cpp | 24 ++-- src/intel/compiler/brw_lower_subgroup_ops.cpp | 18 +-- src/intel/compiler/brw_opt.cpp | 32 ++--- .../compiler/brw_opt_address_reg_load.cpp | 6 +- src/intel/compiler/brw_opt_algebraic.cpp | 6 +- src/intel/compiler/brw_opt_bank_conflicts.cpp | 12 +- .../compiler/brw_opt_cmod_propagation.cpp | 12 +- .../compiler/brw_opt_combine_constants.cpp | 24 ++-- .../compiler/brw_opt_copy_propagation.cpp | 32 ++--- src/intel/compiler/brw_opt_cse.cpp | 24 ++-- .../compiler/brw_opt_dead_code_eliminate.cpp | 8 +- .../compiler/brw_opt_register_coalesce.cpp | 18 +-- .../compiler/brw_opt_saturate_propagation.cpp | 8 +- src/intel/compiler/brw_opt_txf_combiner.cpp | 12 +- src/intel/compiler/brw_opt_virtual_grfs.cpp | 12 +- src/intel/compiler/brw_print.cpp | 10 +- src/intel/compiler/brw_reg_allocate.cpp | 34 ++--- .../compiler/brw_schedule_instructions.cpp | 40 +++--- src/intel/compiler/brw_validate.cpp | 6 +- src/intel/compiler/brw_workaround.cpp | 22 ++-- src/intel/compiler/test_lower_scoreboard.cpp | 72 +++++------ .../compiler/test_opt_cmod_propagation.cpp | 6 +- .../compiler/test_opt_copy_propagation.cpp | 22 ++-- src/intel/compiler/test_opt_cse.cpp | 6 +- .../test_opt_saturate_propagation.cpp | 8 +- 56 files changed, 643 insertions(+), 643 deletions(-) diff --git a/src/intel/compiler/brw_builder.cpp b/src/intel/compiler/brw_builder.cpp index 1562f809bbc..3b46eaf3ff1 100644 --- a/src/intel/compiler/brw_builder.cpp +++ b/src/intel/compiler/brw_builder.cpp @@ -152,7 +152,7 @@ brw_sample_mask_reg(const brw_builder &bld) * Predicate the specified instruction on the sample mask. */ void -brw_emit_predicate_on_sample_mask(const brw_builder &bld, fs_inst *inst) +brw_emit_predicate_on_sample_mask(const brw_builder &bld, brw_inst *inst) { assert(bld.shader->stage == MESA_SHADER_FRAGMENT && bld.group() == inst->group && @@ -248,9 +248,9 @@ brw_check_dynamic_msaa_flag(const brw_builder &bld, const struct brw_wm_prog_data *wm_prog_data, enum intel_msaa_flags flag) { - fs_inst *inst = bld.AND(bld.null_reg_ud(), - brw_dynamic_msaa_flags(wm_prog_data), - brw_imm_ud(flag)); + brw_inst *inst = bld.AND(bld.null_reg_ud(), + brw_dynamic_msaa_flags(wm_prog_data), + brw_imm_ud(flag)); inst->conditional_mod = BRW_CONDITIONAL_NZ; } diff --git a/src/intel/compiler/brw_builder.h b/src/intel/compiler/brw_builder.h index c88bef1c39c..01cafa60dd8 100644 --- a/src/intel/compiler/brw_builder.h +++ b/src/intel/compiler/brw_builder.h @@ -58,7 +58,7 @@ public: * execution controls and debug annotation are initialized from the * instruction passed as argument. */ - brw_builder(fs_visitor *shader, bblock_t *block, fs_inst *inst) : + brw_builder(fs_visitor *shader, bblock_t *block, brw_inst *inst) : shader(shader), block(block), cursor(inst), _dispatch_width(inst->exec_size), _group(inst->group), @@ -255,54 +255,54 @@ public: /** * Insert an instruction into the program. */ - fs_inst * - emit(const fs_inst &inst) const + brw_inst * + emit(const brw_inst &inst) const { - return emit(new(shader->mem_ctx) fs_inst(inst)); + return emit(new(shader->mem_ctx) brw_inst(inst)); } /** * Create and insert a nullary control instruction into the program. */ - fs_inst * + brw_inst * emit(enum opcode opcode) const { - return emit(fs_inst(opcode, dispatch_width())); + return emit(brw_inst(opcode, dispatch_width())); } /** * Create and insert a nullary instruction into the program. */ - fs_inst * + brw_inst * emit(enum opcode opcode, const brw_reg &dst) const { - return emit(fs_inst(opcode, dispatch_width(), dst)); + return emit(brw_inst(opcode, dispatch_width(), dst)); } /** * Create and insert a unary instruction into the program. */ - fs_inst * + brw_inst * emit(enum opcode opcode, const brw_reg &dst, const brw_reg &src0) const { - return emit(fs_inst(opcode, dispatch_width(), dst, src0)); + return emit(brw_inst(opcode, dispatch_width(), dst, src0)); } /** * Create and insert a binary instruction into the program. */ - fs_inst * + brw_inst * emit(enum opcode opcode, const brw_reg &dst, const brw_reg &src0, const brw_reg &src1) const { - return emit(fs_inst(opcode, dispatch_width(), dst, + return emit(brw_inst(opcode, dispatch_width(), dst, src0, src1)); } /** * Create and insert a ternary instruction into the program. */ - fs_inst * + brw_inst * emit(enum opcode opcode, const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, const brw_reg &src2) const { @@ -311,13 +311,13 @@ public: case BRW_OPCODE_BFI2: case BRW_OPCODE_MAD: case BRW_OPCODE_LRP: - return emit(fs_inst(opcode, dispatch_width(), dst, + return emit(brw_inst(opcode, dispatch_width(), dst, fix_3src_operand(src0), fix_3src_operand(src1), fix_3src_operand(src2))); default: - return emit(fs_inst(opcode, dispatch_width(), dst, + return emit(brw_inst(opcode, dispatch_width(), dst, src0, src1, src2)); } } @@ -326,7 +326,7 @@ public: * Create and insert an instruction with a variable number of sources * into the program. */ - fs_inst * + brw_inst * emit(enum opcode opcode, const brw_reg &dst, const brw_reg srcs[], unsigned n) const { @@ -336,15 +336,15 @@ public: if (n == 3) { return emit(opcode, dst, srcs[0], srcs[1], srcs[2]); } else { - return emit(fs_inst(opcode, dispatch_width(), dst, srcs, n)); + return emit(brw_inst(opcode, dispatch_width(), dst, srcs, n)); } } /** * Insert a preallocated instruction into the program. */ - fs_inst * - emit(fs_inst *inst) const + brw_inst * + emit(brw_inst *inst) const { assert(inst->exec_size <= 32); assert(inst->exec_size == dispatch_width() || @@ -357,7 +357,7 @@ public: #endif if (block) - static_cast(cursor)->insert_before(block, inst); + static_cast(cursor)->insert_before(block, inst); else cursor->insert_before(inst); @@ -370,7 +370,7 @@ public: * * Generally useful to get the minimum or maximum of two values. */ - fs_inst * + brw_inst * emit_minmax(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, brw_conditional_mod mod) const { @@ -428,11 +428,11 @@ public: return brw_reg(dst); } - fs_inst * - emit_undef_for_dst(const fs_inst *old_inst) const + brw_inst * + emit_undef_for_dst(const brw_inst *old_inst) const { assert(old_inst->dst.file == VGRF); - fs_inst *inst = emit(SHADER_OPCODE_UNDEF, + brw_inst *inst = emit(SHADER_OPCODE_UNDEF, retype(old_inst->dst, BRW_TYPE_UD)); inst->size_written = old_inst->size_written; @@ -444,7 +444,7 @@ public: * @{ */ #define _ALU1(prefix, op) \ - fs_inst * \ + brw_inst * \ op(const brw_reg &dst, const brw_reg &src0) const \ { \ assert(_dispatch_width == 1 || \ @@ -453,38 +453,38 @@ public: return emit(prefix##op, dst, src0); \ } \ brw_reg \ - op(const brw_reg &src0, fs_inst **out = NULL) const \ + op(const brw_reg &src0, brw_inst **out = NULL) const \ { \ - fs_inst *inst = op(vgrf(src0.type), src0); \ + brw_inst *inst = op(vgrf(src0.type), src0); \ if (out) *out = inst; \ return inst->dst; \ } #define ALU1(op) _ALU1(BRW_OPCODE_, op) #define VIRT1(op) _ALU1(SHADER_OPCODE_, op) - fs_inst * + brw_inst * alu2(opcode op, const brw_reg &dst, const brw_reg &src0, const brw_reg &src1) const { return emit(op, dst, src0, src1); } brw_reg - alu2(opcode op, const brw_reg &src0, const brw_reg &src1, fs_inst **out = NULL) const + alu2(opcode op, const brw_reg &src0, const brw_reg &src1, brw_inst **out = NULL) const { enum brw_reg_type inferred_dst_type = brw_type_larger_of(src0.type, src1.type); - fs_inst *inst = alu2(op, vgrf(inferred_dst_type), src0, src1); + brw_inst *inst = alu2(op, vgrf(inferred_dst_type), src0, src1); if (out) *out = inst; return inst->dst; } #define _ALU2(prefix, op) \ - fs_inst * \ + brw_inst * \ op(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1) const \ { \ return alu2(prefix##op, dst, src0, src1); \ } \ brw_reg \ - op(const brw_reg &src0, const brw_reg &src1, fs_inst **out = NULL) const \ + op(const brw_reg &src0, const brw_reg &src1, brw_inst **out = NULL) const \ { \ return alu2(prefix##op, src0, src1, out); \ } @@ -492,16 +492,16 @@ public: #define VIRT2(op) _ALU2(SHADER_OPCODE_, op) #define ALU2_ACC(op) \ - fs_inst * \ + brw_inst * \ op(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1) const \ { \ - fs_inst *inst = emit(BRW_OPCODE_##op, dst, src0, src1); \ + brw_inst *inst = emit(BRW_OPCODE_##op, dst, src0, src1); \ inst->writes_accumulator = true; \ return inst; \ } #define ALU3(op) \ - fs_inst * \ + brw_inst * \ op(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, \ const brw_reg &src2) const \ { \ @@ -509,12 +509,12 @@ public: } \ brw_reg \ op(const brw_reg &src0, const brw_reg &src1, const brw_reg &src2, \ - fs_inst **out = NULL) const \ + brw_inst **out = NULL) const \ { \ enum brw_reg_type inferred_dst_type = \ brw_type_larger_of(brw_type_larger_of(src0.type, src1.type),\ src2.type); \ - fs_inst *inst = op(vgrf(inferred_dst_type), src0, src1, src2); \ + brw_inst *inst = op(vgrf(inferred_dst_type), src0, src1, src2); \ if (out) *out = inst; \ return inst->dst; \ } @@ -580,14 +580,14 @@ public: #undef _ALU1 /** @} */ - fs_inst * + brw_inst * ADD(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1) const { return alu2(BRW_OPCODE_ADD, dst, src0, src1); } brw_reg - ADD(const brw_reg &src0, const brw_reg &src1, fs_inst **out = NULL) const + ADD(const brw_reg &src0, const brw_reg &src1, brw_inst **out = NULL) const { if (src1.file == IMM && src1.ud == 0 && !out) return src0; @@ -600,7 +600,7 @@ public: * of the comparison, while the upper bits are undefined, and updates * the flag register with the packed 16 bits of the result. */ - fs_inst * + brw_inst * CMP(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, brw_conditional_mod condition) const { @@ -626,7 +626,7 @@ public: /** * CMPN: Behaves like CMP, but produces true if src1 is NaN. */ - fs_inst * + brw_inst * CMPN(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, brw_conditional_mod condition) const { @@ -652,7 +652,7 @@ public: /** * Gfx4 predicated IF. */ - fs_inst * + brw_inst * IF(brw_predicate predicate) const { return set_predicate(predicate, emit(BRW_OPCODE_IF)); @@ -661,7 +661,7 @@ public: /** * CSEL: dst = src2 0.0f ? src0 : src1 */ - fs_inst * + brw_inst * CSEL(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, const brw_reg &src2, brw_conditional_mod condition) const { @@ -676,7 +676,7 @@ public: /** * Emit a linear interpolation instruction. */ - fs_inst * + brw_inst * LRP(const brw_reg &dst, const brw_reg &x, const brw_reg &y, const brw_reg &a) const { @@ -702,11 +702,11 @@ public: /** * Collect a number of registers in a contiguous range of registers. */ - fs_inst * + brw_inst * LOAD_PAYLOAD(const brw_reg &dst, const brw_reg *src, unsigned sources, unsigned header_size) const { - fs_inst *inst = emit(SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources); + brw_inst *inst = emit(SHADER_OPCODE_LOAD_PAYLOAD, dst, src, sources); inst->header_size = header_size; inst->size_written = header_size * REG_SIZE; for (unsigned i = header_size; i < sources; i++) { @@ -717,32 +717,32 @@ public: return inst; } - fs_inst * + brw_inst * VEC(const brw_reg &dst, const brw_reg *src, unsigned sources) const { return sources == 1 ? MOV(dst, src[0]) : LOAD_PAYLOAD(dst, src, sources, 0); } - fs_inst * + brw_inst * SYNC(enum tgl_sync_function sync) const { return emit(BRW_OPCODE_SYNC, null_reg_ud(), brw_imm_ud(sync)); } - fs_inst * + brw_inst * UNDEF(const brw_reg &dst) const { assert(dst.file == VGRF); assert(dst.offset % REG_SIZE == 0); - fs_inst *inst = emit(SHADER_OPCODE_UNDEF, + brw_inst *inst = emit(SHADER_OPCODE_UNDEF, retype(dst, BRW_TYPE_UD)); inst->size_written = shader->alloc.sizes[dst.nr] * REG_SIZE - dst.offset; return inst; } - fs_inst * + brw_inst * DPAS(const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, const brw_reg &src2, unsigned sdepth, unsigned rcount) const { @@ -750,7 +750,7 @@ public: assert(sdepth == 8); assert(rcount == 1 || rcount == 2 || rcount == 4 || rcount == 8); - fs_inst *inst = emit(BRW_OPCODE_DPAS, dst, src0, src1, src2); + brw_inst *inst = emit(BRW_OPCODE_DPAS, dst, src0, src1, src2); inst->sdepth = sdepth; inst->rcount = rcount; @@ -794,7 +794,7 @@ public: srcs[PULL_VARYING_CONSTANT_SRC_OFFSET] = total_offset; srcs[PULL_VARYING_CONSTANT_SRC_ALIGNMENT] = brw_imm_ud(alignment); - fs_inst *inst = emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, + brw_inst *inst = emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, vec4_result, srcs, PULL_VARYING_CONSTANT_SRCS); inst->size_written = 4 * vec4_result.component_size(inst->exec_size); @@ -850,12 +850,12 @@ public: fs_visitor *shader; - fs_inst *BREAK() { return emit(BRW_OPCODE_BREAK); } - fs_inst *DO() { return emit(BRW_OPCODE_DO); } - fs_inst *ENDIF() { return emit(BRW_OPCODE_ENDIF); } - fs_inst *NOP() { return emit(BRW_OPCODE_NOP); } - fs_inst *WHILE() { return emit(BRW_OPCODE_WHILE); } - fs_inst *CONTINUE() { return emit(BRW_OPCODE_CONTINUE); } + brw_inst *BREAK() { return emit(BRW_OPCODE_BREAK); } + brw_inst *DO() { return emit(BRW_OPCODE_DO); } + brw_inst *ENDIF() { return emit(BRW_OPCODE_ENDIF); } + brw_inst *NOP() { return emit(BRW_OPCODE_NOP); } + brw_inst *WHILE() { return emit(BRW_OPCODE_WHILE); } + brw_inst *CONTINUE() { return emit(BRW_OPCODE_CONTINUE); } bool has_writemask_all() const { return force_writemask_all; @@ -961,7 +961,7 @@ offset(const brw_reg ®, const brw_builder &bld, unsigned delta) } brw_reg brw_sample_mask_reg(const brw_builder &bld); -void brw_emit_predicate_on_sample_mask(const brw_builder &bld, fs_inst *inst); +void brw_emit_predicate_on_sample_mask(const brw_builder &bld, brw_inst *inst); brw_reg brw_fetch_payload_reg(const brw_builder &bld, uint8_t regs[2], diff --git a/src/intel/compiler/brw_cfg.cpp b/src/intel/compiler/brw_cfg.cpp index b1cd0292533..8af34c76cea 100644 --- a/src/intel/compiler/brw_cfg.cpp +++ b/src/intel/compiler/brw_cfg.cpp @@ -106,7 +106,7 @@ bblock_t::is_successor_of(const bblock_t *block, } static bool -ends_block(const fs_inst *inst) +ends_block(const brw_inst *inst) { enum opcode op = inst->opcode; @@ -119,7 +119,7 @@ ends_block(const fs_inst *inst) } static bool -starts_block(const fs_inst *inst) +starts_block(const brw_inst *inst) { enum opcode op = inst->opcode; @@ -160,7 +160,7 @@ bblock_t::dump(FILE *file) const const fs_visitor *s = this->cfg->s; int ip = this->start_ip; - foreach_inst_in_block(fs_inst, inst, this) { + foreach_inst_in_block(brw_inst, inst, this) { fprintf(file, "%5d: ", ip); brw_print_instruction(*s, inst, file); ip++; @@ -210,7 +210,7 @@ cfg_t::cfg_t(const fs_visitor *s, exec_list *instructions) : set_next_block(&cur, entry, ip); - foreach_in_list_safe(fs_inst, inst, instructions) { + foreach_in_list_safe(brw_inst, inst, instructions) { /* set_next_block wants the post-incremented ip */ ip++; @@ -808,7 +808,7 @@ cfg_t::validate(const char *stage_abbrev) } } - fs_inst *first_inst = block->start(); + brw_inst *first_inst = block->start(); if (first_inst->opcode == BRW_OPCODE_DO) { /* DO instructions both begin and end a block, so the DO instruction * must be the only instruction in the block. diff --git a/src/intel/compiler/brw_cfg.h b/src/intel/compiler/brw_cfg.h index 0c767e5d274..d7a6cc66cfd 100644 --- a/src/intel/compiler/brw_cfg.h +++ b/src/intel/compiler/brw_cfg.h @@ -90,10 +90,10 @@ struct bblock_t { void combine_with(bblock_t *that); void dump(FILE *file = stderr) const; - fs_inst *start(); - const fs_inst *start() const; - fs_inst *end(); - const fs_inst *end() const; + brw_inst *start(); + const brw_inst *start() const; + brw_inst *end(); + const brw_inst *end() const; bblock_t *next(); const bblock_t *next() const; @@ -103,8 +103,8 @@ struct bblock_t { bool starts_with_control_flow() const; bool ends_with_control_flow() const; - fs_inst *first_non_control_flow_inst(); - fs_inst *last_non_control_flow_inst(); + brw_inst *first_non_control_flow_inst(); + brw_inst *last_non_control_flow_inst(); private: /** @@ -140,28 +140,28 @@ public: int num; }; -static inline fs_inst * +static inline brw_inst * bblock_start(struct bblock_t *block) { - return (fs_inst *)exec_list_get_head(&block->instructions); + return (brw_inst *)exec_list_get_head(&block->instructions); } -static inline const fs_inst * +static inline const brw_inst * bblock_start_const(const struct bblock_t *block) { - return (const fs_inst *)exec_list_get_head_const(&block->instructions); + return (const brw_inst *)exec_list_get_head_const(&block->instructions); } -static inline fs_inst * +static inline brw_inst * bblock_end(struct bblock_t *block) { - return (fs_inst *)exec_list_get_tail(&block->instructions); + return (brw_inst *)exec_list_get_tail(&block->instructions); } -static inline const fs_inst * +static inline const brw_inst * bblock_end_const(const struct bblock_t *block) { - return (const fs_inst *)exec_list_get_tail_const(&block->instructions); + return (const brw_inst *)exec_list_get_tail_const(&block->instructions); } static inline struct bblock_t * @@ -218,51 +218,51 @@ bblock_ends_with_control_flow(const struct bblock_t *block) op == BRW_OPCODE_CONTINUE; } -static inline fs_inst * +static inline brw_inst * bblock_first_non_control_flow_inst(struct bblock_t *block) { - fs_inst *inst = bblock_start(block); + brw_inst *inst = bblock_start(block); if (bblock_starts_with_control_flow(block)) #ifdef __cplusplus - inst = (fs_inst *)inst->next; + inst = (brw_inst *)inst->next; #else - inst = (fs_inst *)inst->link.next; + inst = (brw_inst *)inst->link.next; #endif return inst; } -static inline fs_inst * +static inline brw_inst * bblock_last_non_control_flow_inst(struct bblock_t *block) { - fs_inst *inst = bblock_end(block); + brw_inst *inst = bblock_end(block); if (bblock_ends_with_control_flow(block)) #ifdef __cplusplus - inst = (fs_inst *)inst->prev; + inst = (brw_inst *)inst->prev; #else - inst = (fs_inst *)inst->link.prev; + inst = (brw_inst *)inst->link.prev; #endif return inst; } -inline fs_inst * +inline brw_inst * bblock_t::start() { return bblock_start(this); } -inline const fs_inst * +inline const brw_inst * bblock_t::start() const { return bblock_start_const(this); } -inline fs_inst * +inline brw_inst * bblock_t::end() { return bblock_end(this); } -inline const fs_inst * +inline const brw_inst * bblock_t::end() const { return bblock_end_const(this); @@ -304,13 +304,13 @@ bblock_t::ends_with_control_flow() const return bblock_ends_with_control_flow(this); } -inline fs_inst * +inline brw_inst * bblock_t::first_non_control_flow_inst() { return bblock_first_non_control_flow_inst(this); } -inline fs_inst * +inline brw_inst * bblock_t::last_non_control_flow_inst() { return bblock_last_non_control_flow_inst(this); diff --git a/src/intel/compiler/brw_compile_fs.cpp b/src/intel/compiler/brw_compile_fs.cpp index 31d9e312139..6a5b5aec91a 100644 --- a/src/intel/compiler/brw_compile_fs.cpp +++ b/src/intel/compiler/brw_compile_fs.cpp @@ -20,7 +20,7 @@ using namespace brw; -static fs_inst * +static brw_inst * brw_emit_single_fb_write(fs_visitor &s, const brw_builder &bld, brw_reg color0, brw_reg color1, brw_reg src0_alpha, unsigned components, @@ -47,7 +47,7 @@ brw_emit_single_fb_write(fs_visitor &s, const brw_builder &bld, if (s.nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL)) sources[FB_WRITE_LOGICAL_SRC_SRC_STENCIL] = s.frag_stencil; - fs_inst *write = bld.emit(FS_OPCODE_FB_WRITE_LOGICAL, brw_reg(), + brw_inst *write = bld.emit(FS_OPCODE_FB_WRITE_LOGICAL, brw_reg(), sources, ARRAY_SIZE(sources)); if (prog_data->uses_kill) { @@ -62,7 +62,7 @@ static void brw_do_emit_fb_writes(fs_visitor &s, int nr_color_regions, bool replicate_alpha) { const brw_builder bld = brw_builder(&s).at_end(); - fs_inst *inst = NULL; + brw_inst *inst = NULL; for (int target = 0; target < nr_color_regions; target++) { /* Skip over outputs that weren't written. */ @@ -378,9 +378,9 @@ brw_emit_interpolation_setup(fs_visitor &s) int_pixel_offset_y); if (wm_prog_data->coarse_pixel_dispatch != INTEL_NEVER) { - fs_inst *addx = dbld.ADD(int_pixel_x, int_pixel_x, + brw_inst *addx = dbld.ADD(int_pixel_x, int_pixel_x, horiz_stride(half_int_pixel_offset_x, 0)); - fs_inst *addy = dbld.ADD(int_pixel_y, int_pixel_y, + brw_inst *addy = dbld.ADD(int_pixel_y, int_pixel_y, horiz_stride(half_int_pixel_offset_y, 0)); if (wm_prog_data->coarse_pixel_dispatch != INTEL_ALWAYS) { addx->predicate = BRW_PREDICATE_NORMAL; @@ -608,7 +608,7 @@ static void brw_emit_repclear_shader(fs_visitor &s) { brw_wm_prog_key *key = (brw_wm_prog_key*) s.key; - fs_inst *write = NULL; + brw_inst *write = NULL; assert(s.devinfo->ver < 20); assert(s.uniforms == 0); @@ -1284,7 +1284,7 @@ brw_assign_urb_setup(fs_visitor &s) /* Offset all the urb_setup[] index by the actual position of the * setup regs, now that the location of the constants has been chosen. */ - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == ATTR) { /* ATTR brw_reg::nr in the FS is in units of logical scalar diff --git a/src/intel/compiler/brw_compile_gs.cpp b/src/intel/compiler/brw_compile_gs.cpp index 14a577bb4ce..65beda418a2 100644 --- a/src/intel/compiler/brw_compile_gs.cpp +++ b/src/intel/compiler/brw_compile_gs.cpp @@ -43,7 +43,7 @@ brw_emit_gs_thread_end(fs_visitor &s) } const brw_builder abld = brw_builder(&s).at_end().annotate("thread end"); - fs_inst *inst; + brw_inst *inst; if (gs_prog_data->static_vertex_count != -1) { /* Try and tag the last URB write with EOT instead of emitting a whole @@ -79,7 +79,7 @@ brw_assign_gs_urb_setup(fs_visitor &s) s.first_non_payload_grf += 8 * vue_prog_data->urb_read_length * s.nir->info.gs.vertices_in; - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { /* Rewrite all ATTR file references to GRFs. */ s.convert_attr_sources_to_hw_regs(inst); } diff --git a/src/intel/compiler/brw_compile_mesh.cpp b/src/intel/compiler/brw_compile_mesh.cpp index 59e38b37259..345dc132666 100644 --- a/src/intel/compiler/brw_compile_mesh.cpp +++ b/src/intel/compiler/brw_compile_mesh.cpp @@ -338,7 +338,7 @@ brw_emit_urb_fence(fs_visitor &s) { const brw_builder bld1 = brw_builder(&s).at_end().exec_all().group(1, 0); brw_reg dst = bld1.vgrf(BRW_TYPE_UD); - fs_inst *fence = bld1.emit(SHADER_OPCODE_MEMORY_FENCE, dst, + brw_inst *fence = bld1.emit(SHADER_OPCODE_MEMORY_FENCE, dst, brw_vec8_grf(0, 0), brw_imm_ud(true), brw_imm_ud(0)); diff --git a/src/intel/compiler/brw_compile_tcs.cpp b/src/intel/compiler/brw_compile_tcs.cpp index b0380b4523f..8690f1ac43b 100644 --- a/src/intel/compiler/brw_compile_tcs.cpp +++ b/src/intel/compiler/brw_compile_tcs.cpp @@ -111,7 +111,7 @@ brw_emit_tcs_thread_end(fs_visitor &s) srcs[URB_LOGICAL_SRC_CHANNEL_MASK] = brw_imm_ud(WRITEMASK_X << 16); srcs[URB_LOGICAL_SRC_DATA] = brw_imm_ud(0); srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(1); - fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, + brw_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->eot = true; } @@ -122,7 +122,7 @@ brw_assign_tcs_urb_setup(fs_visitor &s) assert(s.stage == MESA_SHADER_TESS_CTRL); /* Rewrite all ATTR file references to HW_REGs. */ - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { s.convert_attr_sources_to_hw_regs(inst); } } diff --git a/src/intel/compiler/brw_compile_tes.cpp b/src/intel/compiler/brw_compile_tes.cpp index 96af0d405ee..7fdb7a15b52 100644 --- a/src/intel/compiler/brw_compile_tes.cpp +++ b/src/intel/compiler/brw_compile_tes.cpp @@ -22,7 +22,7 @@ brw_assign_tes_urb_setup(fs_visitor &s) s.first_non_payload_grf += 8 * vue_prog_data->urb_read_length; /* Rewrite all ATTR file references to HW_REGs. */ - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { s.convert_attr_sources_to_hw_regs(inst); } } diff --git a/src/intel/compiler/brw_compile_vs.cpp b/src/intel/compiler/brw_compile_vs.cpp index 83c990668d9..38aa01096d8 100644 --- a/src/intel/compiler/brw_compile_vs.cpp +++ b/src/intel/compiler/brw_compile_vs.cpp @@ -25,7 +25,7 @@ brw_assign_vs_urb_setup(fs_visitor &s) assert(vs_prog_data->base.urb_read_length <= 15); /* Rewrite all ATTR file references to the hw grf that they land in. */ - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { s.convert_attr_sources_to_hw_regs(inst); } } diff --git a/src/intel/compiler/brw_def_analysis.cpp b/src/intel/compiler/brw_def_analysis.cpp index e0a910f7400..1cef35e714a 100644 --- a/src/intel/compiler/brw_def_analysis.cpp +++ b/src/intel/compiler/brw_def_analysis.cpp @@ -29,7 +29,7 @@ * Usage: * * const def_analysis &defs = s.def_analysis.require(); - * fs_inst *def = defs.get(inst->src[i]); // returns NULL if non-SSA + * brw_inst *def = defs.get(inst->src[i]); // returns NULL if non-SSA * bblock_t *block = defs.get_block(inst->src[i]); // block containing def * * Def analysis requires the dominator tree, but not liveness information. @@ -37,7 +37,7 @@ using namespace brw; -static fs_inst *const UNSEEN = (fs_inst *) (uintptr_t) 1; +static brw_inst *const UNSEEN = (brw_inst *) (uintptr_t) 1; void def_analysis::mark_invalid(int nr) @@ -49,7 +49,7 @@ def_analysis::mark_invalid(int nr) void def_analysis::update_for_reads(const idom_tree &idom, bblock_t *block, - fs_inst *inst) + brw_inst *inst) { /* We don't track accumulator use for def analysis, so if an instruction * implicitly reads the accumulator, we don't consider it to produce a def. @@ -96,7 +96,7 @@ def_analysis::update_for_reads(const idom_tree &idom, } bool -def_analysis::fully_defines(const fs_visitor *v, fs_inst *inst) +def_analysis::fully_defines(const fs_visitor *v, brw_inst *inst) { return v->alloc.sizes[inst->dst.nr] * REG_SIZE == inst->size_written && !inst->is_partial_write(); @@ -105,7 +105,7 @@ def_analysis::fully_defines(const fs_visitor *v, fs_inst *inst) void def_analysis::update_for_write(const fs_visitor *v, bblock_t *block, - fs_inst *inst) + brw_inst *inst) { const int nr = inst->dst.nr; @@ -132,14 +132,14 @@ def_analysis::def_analysis(const fs_visitor *v) def_count = v->alloc.count; - def_insts = new fs_inst*[def_count](); + def_insts = new brw_inst*[def_count](); def_blocks = new bblock_t*[def_count](); def_use_counts = new uint32_t[def_count](); for (unsigned i = 0; i < def_count; i++) def_insts[i] = UNSEEN; - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { + foreach_block_and_inst(block, brw_inst, inst, v->cfg) { if (inst->opcode != SHADER_OPCODE_UNDEF) { update_for_reads(idom, block, inst); update_for_write(v, block, inst); @@ -155,7 +155,7 @@ def_analysis::def_analysis(const fs_visitor *v) if (def_insts[d] == UNSEEN) def_insts[d] = NULL; - fs_inst *def = def_insts[d]; + brw_inst *def = def_insts[d]; if (!def) continue; diff --git a/src/intel/compiler/brw_disasm_info.cpp b/src/intel/compiler/brw_disasm_info.cpp index ce83840159a..aec389ede08 100644 --- a/src/intel/compiler/brw_disasm_info.cpp +++ b/src/intel/compiler/brw_disasm_info.cpp @@ -116,7 +116,7 @@ disasm_new_inst_group(struct disasm_info *disasm, int next_inst_offset) void disasm_annotate(struct disasm_info *disasm, - fs_inst *inst, int offset) + brw_inst *inst, int offset) { const struct cfg_t *cfg = disasm->cfg; diff --git a/src/intel/compiler/brw_disasm_info.h b/src/intel/compiler/brw_disasm_info.h index 7cd5bd0b05b..3e3aa654659 100644 --- a/src/intel/compiler/brw_disasm_info.h +++ b/src/intel/compiler/brw_disasm_info.h @@ -30,7 +30,7 @@ extern "C" { #endif struct cfg_t; -struct fs_inst; +struct brw_inst; struct intel_device_info; struct inst_group { @@ -75,7 +75,7 @@ disasm_new_inst_group(struct disasm_info *disasm, int offset); void disasm_annotate(struct disasm_info *disasm, - struct fs_inst *inst, int offset); + struct brw_inst *inst, int offset); void disasm_insert_error(struct disasm_info *disasm, int offset, diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 770c6901738..98785c2af5f 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -157,7 +157,7 @@ brw_barycentric_mode(const struct brw_wm_prog_key *key, bool fs_visitor::mark_last_urb_write_with_eot() { - foreach_in_list_reverse(fs_inst, prev, &this->instructions) { + foreach_in_list_reverse(brw_inst, prev, &this->instructions) { if (prev->opcode == SHADER_OPCODE_URB_WRITE_LOGICAL) { prev->eot = true; @@ -243,7 +243,7 @@ fs_visitor::assign_curb_setup() brw_reg dest = retype(brw_vec8_grf(payload().num_regs + i, 0), BRW_TYPE_UD); - fs_inst *send = ubld.emit(SHADER_OPCODE_SEND, dest, srcs, 4); + brw_inst *send = ubld.emit(SHADER_OPCODE_SEND, dest, srcs, 4); send->sfid = GFX12_SFID_UGM; uint32_t desc = lsc_msg_desc(devinfo, LSC_OP_LOAD, @@ -272,7 +272,7 @@ fs_visitor::assign_curb_setup() } /* Map the offsets in the UNIFORM file to fixed HW regs. */ - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, brw_inst, inst, cfg) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == UNIFORM) { int uniform_nr = inst->src[i].nr + inst->src[i].offset / 4; @@ -378,7 +378,7 @@ brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data) } void -fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst) +fs_visitor::convert_attr_sources_to_hw_regs(brw_inst *inst) { for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == ATTR) { @@ -437,7 +437,7 @@ brw_get_subgroup_id_param_index(const intel_device_info *devinfo, } uint32_t -brw_fb_write_msg_control(const fs_inst *inst, +brw_fb_write_msg_control(const brw_inst *inst, const struct brw_wm_prog_data *prog_data) { uint32_t mctl; @@ -544,25 +544,25 @@ brw_compute_max_register_pressure(fs_visitor &s) { const register_pressure &rp = s.regpressure_analysis.require(); uint32_t ip = 0, max_pressure = 0; - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { max_pressure = MAX2(max_pressure, rp.regs_live_at_ip[ip]); ip++; } return max_pressure; } -static fs_inst ** +static brw_inst ** save_instruction_order(const struct cfg_t *cfg) { /* Before we schedule anything, stash off the instruction order as an array - * of fs_inst *. This way, we can reset it between scheduling passes to + * of brw_inst *. This way, we can reset it between scheduling passes to * prevent dependencies between the different scheduling modes. */ int num_insts = cfg->last_block()->end_ip + 1; - fs_inst **inst_arr = new fs_inst * [num_insts]; + brw_inst **inst_arr = new brw_inst * [num_insts]; int ip = 0; - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, brw_inst, inst, cfg) { assert(ip >= block->start_ip && ip <= block->end_ip); inst_arr[ip++] = inst; } @@ -572,7 +572,7 @@ save_instruction_order(const struct cfg_t *cfg) } static void -restore_instruction_order(struct cfg_t *cfg, fs_inst **inst_arr) +restore_instruction_order(struct cfg_t *cfg, brw_inst **inst_arr) { ASSERTED int num_insts = cfg->last_block()->end_ip + 1; @@ -629,11 +629,11 @@ brw_allocate_registers(fs_visitor &s, bool allow_spilling) bool spill_all = allow_spilling && INTEL_DEBUG(DEBUG_SPILL_FS); /* Before we schedule anything, stash off the instruction order as an array - * of fs_inst *. This way, we can reset it between scheduling passes to + * of brw_inst *. This way, we can reset it between scheduling passes to * prevent dependencies between the different scheduling modes. */ - fs_inst **orig_order = save_instruction_order(s.cfg); - fs_inst **best_pressure_order = NULL; + brw_inst **orig_order = save_instruction_order(s.cfg); + brw_inst **best_pressure_order = NULL; void *scheduler_ctx = ralloc_context(NULL); brw_instruction_scheduler *sched = brw_prepare_scheduler(s, scheduler_ctx); diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 8cc58a80c27..55dafe5d8f5 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -74,7 +74,7 @@ namespace brw { def_analysis(const fs_visitor *v); ~def_analysis(); - fs_inst * + brw_inst * get(const brw_reg ®) const { return reg.file == VGRF && reg.nr < def_count ? @@ -113,11 +113,11 @@ namespace brw { private: void mark_invalid(int); - bool fully_defines(const fs_visitor *v, fs_inst *); - void update_for_reads(const idom_tree &idom, bblock_t *block, fs_inst *); - void update_for_write(const fs_visitor *v, bblock_t *block, fs_inst *); + bool fully_defines(const fs_visitor *v, brw_inst *); + void update_for_reads(const idom_tree &idom, bblock_t *block, brw_inst *); + void update_for_write(const fs_visitor *v, bblock_t *block, brw_inst *); - fs_inst **def_insts; + brw_inst **def_insts; bblock_t **def_blocks; uint32_t *def_use_counts; unsigned def_count; @@ -296,7 +296,7 @@ public: void import_uniforms(fs_visitor *v); void assign_curb_setup(); - void convert_attr_sources_to_hw_regs(fs_inst *inst); + void convert_attr_sources_to_hw_regs(brw_inst *inst); void calculate_payload_ranges(bool allow_spilling, unsigned payload_node_count, int *payload_last_use_ip) const; @@ -322,7 +322,7 @@ public: /** ralloc context for temporary data used during compile */ void *mem_ctx; - /** List of fs_inst. */ + /** List of brw_inst. */ exec_list instructions; cfg_t *cfg; @@ -447,7 +447,7 @@ public: void brw_print_instructions(const fs_visitor &s, FILE *file = stderr); -void brw_print_instruction(const fs_visitor &s, const fs_inst *inst, +void brw_print_instruction(const fs_visitor &s, const brw_inst *inst, FILE *file = stderr, const brw::def_analysis *defs = nullptr); @@ -474,7 +474,7 @@ brw_dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data) enum intel_barycentric_mode brw_barycentric_mode(const struct brw_wm_prog_key *key, nir_intrinsic_instr *intr); -uint32_t brw_fb_write_msg_control(const fs_inst *inst, +uint32_t brw_fb_write_msg_control(const brw_inst *inst, const struct brw_wm_prog_data *prog_data); void brw_compute_urb_setup_index(struct brw_wm_prog_data *wm_prog_data); @@ -536,7 +536,7 @@ bool brw_lower_send_descriptors(fs_visitor &s); bool brw_lower_send_gather(fs_visitor &s); bool brw_lower_sends_overlapping_payload(fs_visitor &s); bool brw_lower_simd_width(fs_visitor &s); -bool brw_lower_src_modifiers(fs_visitor &s, bblock_t *block, fs_inst *inst, unsigned i); +bool brw_lower_src_modifiers(fs_visitor &s, bblock_t *block, brw_inst *inst, unsigned i); bool brw_lower_sub_sat(fs_visitor &s); bool brw_lower_subgroup_ops(fs_visitor &s); bool brw_lower_uniform_pull_constant_loads(fs_visitor &s); @@ -549,7 +549,7 @@ bool brw_opt_cmod_propagation(fs_visitor &s); bool brw_opt_combine_constants(fs_visitor &s); bool brw_opt_combine_convergent_txf(fs_visitor &s); bool brw_opt_compact_virtual_grfs(fs_visitor &s); -bool brw_opt_constant_fold_instruction(const intel_device_info *devinfo, fs_inst *inst); +bool brw_opt_constant_fold_instruction(const intel_device_info *devinfo, brw_inst *inst); bool brw_opt_copy_propagation(fs_visitor &s); bool brw_opt_copy_propagation_defs(fs_visitor &s); bool brw_opt_cse_defs(fs_visitor &s); @@ -572,4 +572,4 @@ bool brw_workaround_source_arf_before_eot(fs_visitor &s); /* Helpers. */ unsigned brw_get_lowered_simd_width(const fs_visitor *shader, - const fs_inst *inst); + const brw_inst *inst); diff --git a/src/intel/compiler/brw_fs_live_variables.cpp b/src/intel/compiler/brw_fs_live_variables.cpp index 6197fa59d97..7336833ca6f 100644 --- a/src/intel/compiler/brw_fs_live_variables.cpp +++ b/src/intel/compiler/brw_fs_live_variables.cpp @@ -71,7 +71,7 @@ fs_live_variables::setup_one_read(struct block_data *bd, } void -fs_live_variables::setup_one_write(struct block_data *bd, fs_inst *inst, +fs_live_variables::setup_one_write(struct block_data *bd, brw_inst *inst, int ip, const brw_reg ®) { int var = var_from_reg(reg); @@ -112,7 +112,7 @@ fs_live_variables::setup_def_use() struct block_data *bd = &block_data[block->num]; - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(brw_inst, inst, block) { /* Set use[] for this instruction */ for (unsigned int i = 0; i < inst->sources; i++) { brw_reg reg = inst->src[i]; @@ -338,7 +338,7 @@ fs_live_variables::validate(const fs_visitor *s) const { int ip = 0; - foreach_block_and_inst(block, fs_inst, inst, s->cfg) { + foreach_block_and_inst(block, brw_inst, inst, s->cfg) { for (unsigned i = 0; i < inst->sources; i++) { if (inst->src[i].file == VGRF && !check_register_live_range(this, ip, diff --git a/src/intel/compiler/brw_fs_live_variables.h b/src/intel/compiler/brw_fs_live_variables.h index 496930c4bc8..8fd07d4543a 100644 --- a/src/intel/compiler/brw_fs_live_variables.h +++ b/src/intel/compiler/brw_fs_live_variables.h @@ -132,7 +132,7 @@ public: protected: void setup_def_use(); void setup_one_read(struct block_data *bd, int ip, const brw_reg ®); - void setup_one_write(struct block_data *bd, fs_inst *inst, int ip, + void setup_one_write(struct block_data *bd, brw_inst *inst, int ip, const brw_reg ®); void compute_live_variables(); void compute_start_end(); diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 121e0f777b8..fe787e22587 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -435,11 +435,11 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) } /* first, put the condition into f0 */ - fs_inst *inst = bld.MOV(bld.null_reg_d(), + brw_inst *inst = bld.MOV(bld.null_reg_d(), retype(cond_reg, BRW_TYPE_D)); inst->conditional_mod = BRW_CONDITIONAL_NZ; - fs_inst *iff = bld.IF(BRW_PREDICATE_NORMAL); + brw_inst *iff = bld.IF(BRW_PREDICATE_NORMAL); iff->predicate_inverse = invert; fs_nir_emit_cf_list(ntb, &if_stmt->then_list); @@ -449,11 +449,11 @@ fs_nir_emit_if(nir_to_brw_state &ntb, nir_if *if_stmt) fs_nir_emit_cf_list(ntb, &if_stmt->else_list); } - fs_inst *endif = bld.emit(BRW_OPCODE_ENDIF); + brw_inst *endif = bld.emit(BRW_OPCODE_ENDIF); /* Peephole: replace IF-JUMP-ENDIF with predicated jump */ if (endif->prev->prev == iff) { - fs_inst *jump = (fs_inst *) endif->prev; + brw_inst *jump = (brw_inst *) endif->prev; if (jump->predicate == BRW_PREDICATE_NONE && (jump->opcode == BRW_OPCODE_BREAK || jump->opcode == BRW_OPCODE_CONTINUE)) { @@ -475,10 +475,10 @@ fs_nir_emit_loop(nir_to_brw_state &ntb, nir_loop *loop) fs_nir_emit_cf_list(ntb, &loop->body); - fs_inst *peep_while = bld.emit(BRW_OPCODE_WHILE); + brw_inst *peep_while = bld.emit(BRW_OPCODE_WHILE); /* Peephole: replace (+f0) break; while with (-f0) while */ - fs_inst *peep_break = (fs_inst *) peep_while->prev; + brw_inst *peep_break = (brw_inst *) peep_while->prev; if (peep_break->opcode == BRW_OPCODE_BREAK && peep_break->predicate != BRW_PREDICATE_NONE) { @@ -918,7 +918,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, { const intel_device_info *devinfo = ntb.devinfo; - fs_inst *inst; + brw_inst *inst; unsigned execution_mode = ntb.bld.shader->nir->info.float_controls_execution_mode; @@ -1426,7 +1426,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr, /* Smash all of the sources and destination to be signed. This * doesn't matter for the operation of the instruction, but cmod * propagation fails on unsigned sources with negation (due to - * fs_inst::can_do_cmod returning false). + * brw_inst::can_do_cmod returning false). */ result.type = brw_type_for_nir_type(devinfo, @@ -2062,7 +2062,7 @@ get_nir_write_mask(const nir_def &def) } } -static fs_inst * +static brw_inst * emit_pixel_interpolater_send(const brw_builder &bld, enum opcode opcode, const brw_reg &dst, @@ -2086,7 +2086,7 @@ emit_pixel_interpolater_send(const brw_builder &bld, srcs[INTERP_SRC_MSG_DESC] = desc; srcs[INTERP_SRC_DYNAMIC_MODE] = flag_reg; - fs_inst *inst = bld.emit(opcode, dst, srcs, INTERP_NUM_SRCS); + brw_inst *inst = bld.emit(opcode, dst, srcs, INTERP_NUM_SRCS); /* 2 floats per slot returned */ inst->size_written = 2 * dst.component_size(inst->exec_size); if (interpolation == INTERP_MODE_NOPERSPECTIVE) { @@ -2539,7 +2539,7 @@ fs_visitor::emit_gs_control_data_bits(const brw_reg &vertex_count) srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0); - fs_inst *inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + brw_inst *inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); /* We need to increment Global Offset by 256-bits to make room for @@ -2650,7 +2650,7 @@ emit_gs_vertex(nir_to_brw_state &ntb, const nir_src &vertex_count_nir_src, * TODO: If vertex_count is an immediate, we could do some of this math * at compile time... */ - fs_inst *inst = + brw_inst *inst = abld.AND(ntb.bld.null_reg_d(), vertex_count, brw_imm_ud(32u / s.gs_compile->control_data_bits_per_vertex - 1u)); inst->conditional_mod = BRW_CONDITIONAL_Z; @@ -2801,7 +2801,7 @@ emit_gs_input_load(nir_to_brw_state &ntb, const brw_reg &dst, } } - fs_inst *inst; + brw_inst *inst; brw_reg indirect_offset = get_nir_src(ntb, offset_src); if (nir_src_is_const(offset_src)) { @@ -3157,7 +3157,7 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, assert(instr->def.bit_size == 32); brw_reg indirect_offset = get_indirect_offset(ntb, instr); unsigned imm_offset = nir_intrinsic_base(instr); - fs_inst *inst; + brw_inst *inst; const bool multi_patch = vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH; @@ -3230,7 +3230,7 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, unsigned imm_offset = nir_intrinsic_base(instr); unsigned first_component = nir_intrinsic_component(instr); - fs_inst *inst; + brw_inst *inst; if (indirect_offset.file == BAD_FILE) { /* This MOV replicates the output handle to all enabled channels * is SINGLE_PATCH mode. @@ -3327,7 +3327,7 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb, srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(m); bld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, m, 0); - fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + brw_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->offset = imm_offset; break; @@ -3371,7 +3371,7 @@ fs_nir_emit_tes_intrinsic(nir_to_brw_state &ntb, unsigned imm_offset = nir_intrinsic_base(instr); unsigned first_component = nir_intrinsic_component(instr); - fs_inst *inst; + brw_inst *inst; if (indirect_offset.file == BAD_FILE) { /* Arbitrarily only push up to 32 vec4 slots worth of data, * which is 16 registers (since each holds 2 vec4 slots). @@ -3655,7 +3655,7 @@ emit_mcs_fetch(nir_to_brw_state &ntb, const brw_reg &coordinate, unsigned compon srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(0); srcs[TEX_LOGICAL_SRC_RESIDENCY] = brw_imm_d(0); - fs_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs, + brw_inst *inst = bld.emit(SHADER_OPCODE_TXF_MCS_LOGICAL, dest, srcs, ARRAY_SIZE(srcs)); /* We only care about one or two regs of response, but the sampler always @@ -3670,7 +3670,7 @@ emit_mcs_fetch(nir_to_brw_state &ntb, const brw_reg &coordinate, unsigned compon * Fake non-coherent framebuffer read implemented using TXF to fetch from the * framebuffer at the current fragment coordinates and sample index. */ -static fs_inst * +static brw_inst * emit_non_coherent_fb_read(nir_to_brw_state &ntb, const brw_builder &bld, const brw_reg &dst, unsigned target) { @@ -3736,7 +3736,7 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const brw_builder &bld, const b srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_ud(0); srcs[TEX_LOGICAL_SRC_RESIDENCY] = brw_imm_ud(0); - fs_inst *inst = bld.emit(op, dst, srcs, ARRAY_SIZE(srcs)); + brw_inst *inst = bld.emit(op, dst, srcs, ARRAY_SIZE(srcs)); inst->size_written = 4 * inst->dst.component_size(inst->exec_size); return inst; @@ -3746,10 +3746,10 @@ emit_non_coherent_fb_read(nir_to_brw_state &ntb, const brw_builder &bld, const b * Actual coherent framebuffer read implemented using the native render target * read message. Requires SKL+. */ -static fs_inst * +static brw_inst * emit_coherent_fb_read(const brw_builder &bld, const brw_reg &dst, unsigned target) { - fs_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst); + brw_inst *inst = bld.emit(FS_OPCODE_FB_READ_LOGICAL, dst); inst->target = target; inst->size_written = 4 * inst->dst.component_size(inst->exec_size); @@ -3826,7 +3826,7 @@ emit_is_helper_invocation(nir_to_brw_state &ntb, brw_reg result) for (unsigned i = 0; i < DIV_ROUND_UP(width, 16); i++) { const brw_builder b = bld.group(MIN2(width, 16), i); - fs_inst *mov = b.MOV(offset(result, b, i), brw_imm_ud(~0)); + brw_inst *mov = b.MOV(offset(result, b, i), brw_imm_ud(~0)); /* The at() ensures that any code emitted to get the predicate happens * before the mov right above. This is not an issue elsewhere because @@ -4303,7 +4303,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, * no condition, we emit a CMP of g0 != g0, so all currently executing * channels will get turned off. */ - fs_inst *cmp = NULL; + brw_inst *cmp = NULL; if (instr->intrinsic == nir_intrinsic_demote_if || instr->intrinsic == nir_intrinsic_terminate_if) { nir_alu_instr *alu = nir_src_as_alu_instr(instr->src[0]); @@ -4326,7 +4326,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, */ fs_nir_emit_alu(ntb, alu, false); - cmp = (fs_inst *) s.instructions.get_tail(); + cmp = (brw_inst *) s.instructions.get_tail(); if (cmp->conditional_mod == BRW_CONDITIONAL_NONE) { if (cmp->can_do_cmod()) cmp->conditional_mod = BRW_CONDITIONAL_Z; @@ -4373,7 +4373,7 @@ fs_nir_emit_fs_intrinsic(nir_to_brw_state &ntb, cmp->predicate = BRW_PREDICATE_NORMAL; cmp->flag_subreg = sample_mask_flag_subreg(s); - fs_inst *jump = bld.emit(BRW_OPCODE_HALT); + brw_inst *jump = bld.emit(BRW_OPCODE_HALT); jump->flag_subreg = sample_mask_flag_subreg(s); jump->predicate_inverse = true; @@ -4691,7 +4691,7 @@ fs_nir_emit_cs_intrinsic(nir_to_brw_state &ntb, srcs[MEMORY_LOGICAL_COMPONENTS] = brw_imm_ud(3); srcs[MEMORY_LOGICAL_FLAGS] = brw_imm_ud(0); - fs_inst *inst = + brw_inst *inst = bld.emit(SHADER_OPCODE_MEMORY_LOAD_LOGICAL, dest, srcs, MEMORY_LOGICAL_NUM_SRCS); inst->size_written = 3 * s.dispatch_width * 4; @@ -4748,7 +4748,7 @@ emit_rt_lsc_fence(const brw_builder &bld, const brw_builder ubld = bld.exec_all().group(8, 0); brw_reg tmp = ubld.vgrf(BRW_TYPE_UD); - fs_inst *send = ubld.emit(SHADER_OPCODE_SEND, tmp, + brw_inst *send = ubld.emit(SHADER_OPCODE_SEND, tmp, brw_imm_ud(0) /* desc */, brw_imm_ud(0) /* ex_desc */, brw_vec8_grf(0, 0) /* payload */); @@ -4972,7 +4972,7 @@ emit_fence(const brw_builder &bld, enum opcode opcode, opcode == SHADER_OPCODE_MEMORY_FENCE); brw_reg dst = bld.vgrf(BRW_TYPE_UD); - fs_inst *fence = bld.emit(opcode, dst, brw_vec8_grf(0, 0), + brw_inst *fence = bld.emit(opcode, dst, brw_vec8_grf(0, 0), brw_imm_ud(commit_enable), brw_imm_ud(bti)); fence->sfid = sfid; @@ -5091,7 +5091,7 @@ emit_urb_direct_vec4_write(const brw_builder &bld, srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); - fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, + brw_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->offset = urb_global_offset; assert(inst->offset < 2048); @@ -5224,7 +5224,7 @@ emit_urb_indirect_vec4_write(const brw_builder &bld, srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); - fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, + brw_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->offset = 0; } @@ -5355,7 +5355,7 @@ emit_urb_indirect_writes(const brw_builder &bld, nir_intrinsic_instr *instr, srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); bld8.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], payload_srcs, length, 0); - fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, + brw_inst *inst = bld8.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->offset = 0; } @@ -5390,7 +5390,7 @@ emit_urb_direct_reads(const brw_builder &bld, nir_intrinsic_instr *instr, brw_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle; - fs_inst *inst = ubld8.emit(SHADER_OPCODE_URB_READ_LOGICAL, data, + brw_inst *inst = ubld8.emit(SHADER_OPCODE_URB_READ_LOGICAL, data, srcs, ARRAY_SIZE(srcs)); inst->offset = urb_global_offset; assert(inst->offset < 2048); @@ -5429,7 +5429,7 @@ emit_urb_direct_reads_xe2(const brw_builder &bld, nir_intrinsic_instr *instr, brw_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = urb_handle; - fs_inst *inst = ubld16.emit(SHADER_OPCODE_URB_READ_LOGICAL, + brw_inst *inst = ubld16.emit(SHADER_OPCODE_URB_READ_LOGICAL, data, srcs, ARRAY_SIZE(srcs)); inst->size_written = 2 * comps * REG_SIZE; @@ -5489,7 +5489,7 @@ emit_urb_indirect_reads(const brw_builder &bld, nir_intrinsic_instr *instr, brw_reg data = bld8.vgrf(BRW_TYPE_UD, 4); - fs_inst *inst = bld8.emit(SHADER_OPCODE_URB_READ_LOGICAL, + brw_inst *inst = bld8.emit(SHADER_OPCODE_URB_READ_LOGICAL, data, srcs, ARRAY_SIZE(srcs)); inst->offset = 0; inst->size_written = 4 * REG_SIZE; @@ -5535,7 +5535,7 @@ emit_urb_indirect_reads_xe2(const brw_builder &bld, nir_intrinsic_instr *instr, brw_reg srcs[URB_LOGICAL_NUM_SRCS]; srcs[URB_LOGICAL_SRC_HANDLE] = wbld.ADD(addr, urb_handle); - fs_inst *inst = wbld.emit(SHADER_OPCODE_URB_READ_LOGICAL, + brw_inst *inst = wbld.emit(SHADER_OPCODE_URB_READ_LOGICAL, data, srcs, ARRAY_SIZE(srcs)); inst->size_written = 2 * comps * REG_SIZE; @@ -5837,7 +5837,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, const brw_builder ubld = bld.scalar_group(); brw_reg tmp = ubld.vgrf(BRW_TYPE_UD, 4); - fs_inst *inst = ubld.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL, + brw_inst *inst = ubld.emit(SHADER_OPCODE_IMAGE_SIZE_LOGICAL, tmp, srcs, ARRAY_SIZE(srcs)); inst->size_written = 4 * REG_SIZE * reg_unit(devinfo); @@ -6341,7 +6341,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, GET_BUFFER_SIZE_SRC_SURFACE] = get_nir_buffer_intrinsic_index(ntb, bld, instr); srcs[GET_BUFFER_SIZE_SRC_LOD] = src_payload; - fs_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload, + brw_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload, srcs, GET_BUFFER_SIZE_SRCS); inst->header_size = 0; inst->mlen = reg_unit(devinfo); @@ -6471,7 +6471,7 @@ fs_nir_emit_intrinsic(nir_to_brw_state &ntb, * ballot must execute on all SIMD lanes regardless of the amount of * data (i.e., scalar or not scalar) generated. */ - fs_inst *inst = bld.emit(SHADER_OPCODE_BALLOT, dest, value); + brw_inst *inst = bld.emit(SHADER_OPCODE_BALLOT, dest, value); if (dest.is_scalar) inst->size_written = dest.component_size(xbld.dispatch_width()); @@ -7107,7 +7107,7 @@ fs_nir_emit_memory_access(nir_to_brw_state &ntb, instr->intrinsic == nir_intrinsic_store_shared_block_intel || instr->intrinsic == nir_intrinsic_store_ssbo_block_intel; - fs_inst *inst; + brw_inst *inst; if (!block) { inst = xbld.emit(opcode, dest, srcs, MEMORY_LOGICAL_NUM_SRCS); @@ -7531,7 +7531,7 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, bld.shader->alloc.allocate(total_regs * reg_unit(devinfo)), dst_type); - fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs)); + brw_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs)); inst->offset = header_bits; inst->size_written = total_regs * grf_size; @@ -7595,10 +7595,10 @@ fs_nir_emit_texture(nir_to_brw_state &ntb, * When a surface of type SURFTYPE_NULL is accessed by resinfo, the * MIPCount returned is undefined instead of 0. */ - fs_inst *mov = bld.MOV(bld.null_reg_d(), dst); + brw_inst *mov = bld.MOV(bld.null_reg_d(), dst); mov->conditional_mod = BRW_CONDITIONAL_NZ; nir_dest[0] = bld.vgrf(BRW_TYPE_D); - fs_inst *sel = + brw_inst *sel = bld.SEL(nir_dest[0], offset(dst, bld, 3), brw_imm_d(0)); sel->predicate = BRW_PREDICATE_NORMAL; } else { diff --git a/src/intel/compiler/brw_fs_visitor.cpp b/src/intel/compiler/brw_fs_visitor.cpp index 7427f93a9fa..c0bed77a28f 100644 --- a/src/intel/compiler/brw_fs_visitor.cpp +++ b/src/intel/compiler/brw_fs_visitor.cpp @@ -220,7 +220,7 @@ fs_visitor::emit_urb_writes(const brw_reg &gs_vertex_count) srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(length); abld.LOAD_PAYLOAD(srcs[URB_LOGICAL_SRC_DATA], sources, length, 0); - fs_inst *inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + brw_inst *inst = abld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); /* For Wa_1805992985 one needs additional write in the end. */ @@ -267,7 +267,7 @@ fs_visitor::emit_urb_writes(const brw_reg &gs_vertex_count) srcs[URB_LOGICAL_SRC_DATA] = payload; srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(1); - fs_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, + brw_inst *inst = bld.emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->eot = true; inst->offset = 1; @@ -319,7 +319,7 @@ fs_visitor::emit_urb_writes(const brw_reg &gs_vertex_count) srcs[URB_LOGICAL_SRC_DATA] = payload; srcs[URB_LOGICAL_SRC_COMPONENTS] = brw_imm_ud(4); - fs_inst *inst = bld.exec_all().emit(SHADER_OPCODE_URB_WRITE_LOGICAL, + brw_inst *inst = bld.exec_all().emit(SHADER_OPCODE_URB_WRITE_LOGICAL, reg_undef, srcs, ARRAY_SIZE(srcs)); inst->eot = true; inst->offset = 0; @@ -359,7 +359,7 @@ fs_visitor::emit_cs_terminate() brw_reg(), /* payload2 */ }; - fs_inst *send = ubld.emit(SHADER_OPCODE_SEND, reg_undef, srcs, 4); + brw_inst *send = ubld.emit(SHADER_OPCODE_SEND, reg_undef, srcs, 4); /* On Alchemist and later, send an EOT message to the message gateway to * terminate a compute shader. For older GPUs, send to the thread spawner. diff --git a/src/intel/compiler/brw_generator.cpp b/src/intel/compiler/brw_generator.cpp index 9707bda808e..4c3d17cf764 100644 --- a/src/intel/compiler/brw_generator.cpp +++ b/src/intel/compiler/brw_generator.cpp @@ -161,7 +161,7 @@ brw_generator::patch_halt_jumps() } void -brw_generator::generate_send(fs_inst *inst, +brw_generator::generate_send(brw_inst *inst, struct brw_reg dst, struct brw_reg desc, struct brw_reg ex_desc, @@ -194,7 +194,7 @@ brw_generator::generate_send(fs_inst *inst, } void -brw_generator::generate_mov_indirect(fs_inst *inst, +brw_generator::generate_mov_indirect(brw_inst *inst, struct brw_reg dst, struct brw_reg reg, struct brw_reg indirect_byte_offset) @@ -325,7 +325,7 @@ brw_generator::generate_mov_indirect(fs_inst *inst, } void -brw_generator::generate_shuffle(fs_inst *inst, +brw_generator::generate_shuffle(brw_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg idx) @@ -455,7 +455,7 @@ brw_generator::generate_shuffle(fs_inst *inst, } void -brw_generator::generate_quad_swizzle(const fs_inst *inst, +brw_generator::generate_quad_swizzle(const brw_inst *inst, struct brw_reg dst, struct brw_reg src, unsigned swiz) { @@ -525,7 +525,7 @@ brw_generator::generate_quad_swizzle(const fs_inst *inst, } void -brw_generator::generate_barrier(fs_inst *, struct brw_reg src) +brw_generator::generate_barrier(brw_inst *, struct brw_reg src) { brw_barrier(p, src); if (devinfo->ver >= 12) { @@ -565,7 +565,7 @@ brw_generator::generate_barrier(fs_inst *, struct brw_reg src) * appropriate swizzling. */ void -brw_generator::generate_ddx(const fs_inst *inst, +brw_generator::generate_ddx(const brw_inst *inst, struct brw_reg dst, struct brw_reg src) { unsigned vstride, width; @@ -598,7 +598,7 @@ brw_generator::generate_ddx(const fs_inst *inst, * left. */ void -brw_generator::generate_ddy(const fs_inst *inst, +brw_generator::generate_ddy(const brw_inst *inst, struct brw_reg dst, struct brw_reg src) { const uint32_t type_size = brw_type_size_bytes(src.type); @@ -651,7 +651,7 @@ brw_generator::generate_ddy(const fs_inst *inst, } void -brw_generator::generate_halt(fs_inst *) +brw_generator::generate_halt(brw_inst *) { /* This HALT will be patched up at FB write time to point UIP at the end of * the program, and at brw_uip_jip() JIP will be set to the end of the @@ -700,7 +700,7 @@ brw_generator::generate_halt(fs_inst *) * information required by either set of opcodes. */ void -brw_generator::generate_scratch_header(fs_inst *inst, +brw_generator::generate_scratch_header(brw_inst *inst, struct brw_reg dst, struct brw_reg src) { @@ -773,7 +773,7 @@ brw_generator::generate_code(const cfg_t *cfg, int dispatch_width, struct disasm_info *disasm_info = disasm_initialize(p->isa, cfg); enum opcode prev_opcode = BRW_OPCODE_ILLEGAL; - foreach_block_and_inst (block, fs_inst, inst, cfg) { + foreach_block_and_inst (block, brw_inst, inst, cfg) { if (inst->opcode == SHADER_OPCODE_UNDEF) continue; diff --git a/src/intel/compiler/brw_generator.h b/src/intel/compiler/brw_generator.h index 72d01219a8c..048e625d771 100644 --- a/src/intel/compiler/brw_generator.h +++ b/src/intel/compiler/brw_generator.h @@ -28,33 +28,33 @@ public: const unsigned *get_assembly(); private: - void generate_send(fs_inst *inst, + void generate_send(brw_inst *inst, struct brw_reg dst, struct brw_reg desc, struct brw_reg ex_desc, struct brw_reg payload, struct brw_reg payload2); - void generate_barrier(fs_inst *inst, struct brw_reg src); - void generate_ddx(const fs_inst *inst, + void generate_barrier(brw_inst *inst, struct brw_reg src); + void generate_ddx(const brw_inst *inst, struct brw_reg dst, struct brw_reg src); - void generate_ddy(const fs_inst *inst, + void generate_ddy(const brw_inst *inst, struct brw_reg dst, struct brw_reg src); - void generate_scratch_header(fs_inst *inst, + void generate_scratch_header(brw_inst *inst, struct brw_reg dst, struct brw_reg src); - void generate_halt(fs_inst *inst); + void generate_halt(brw_inst *inst); - void generate_mov_indirect(fs_inst *inst, + void generate_mov_indirect(brw_inst *inst, struct brw_reg dst, struct brw_reg reg, struct brw_reg indirect_byte_offset); - void generate_shuffle(fs_inst *inst, + void generate_shuffle(brw_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg idx); - void generate_quad_swizzle(const fs_inst *inst, + void generate_quad_swizzle(const brw_inst *inst, struct brw_reg dst, struct brw_reg src, unsigned swiz); diff --git a/src/intel/compiler/brw_inst.cpp b/src/intel/compiler/brw_inst.cpp index 16f1c336dd7..478ca7ac493 100644 --- a/src/intel/compiler/brw_inst.cpp +++ b/src/intel/compiler/brw_inst.cpp @@ -10,10 +10,10 @@ #include "brw_isa_info.h" static void -initialize_sources(fs_inst *inst, const brw_reg src[], uint8_t num_sources); +initialize_sources(brw_inst *inst, const brw_reg src[], uint8_t num_sources); void -fs_inst::init(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, +brw_inst::init(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, const brw_reg *src, unsigned sources) { memset((void*)this, 0, sizeof(*this)); @@ -53,62 +53,62 @@ fs_inst::init(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, this->writes_accumulator = false; } -fs_inst::fs_inst() +brw_inst::brw_inst() { init(BRW_OPCODE_NOP, 8, dst, NULL, 0); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size) +brw_inst::brw_inst(enum opcode opcode, uint8_t exec_size) { init(opcode, exec_size, reg_undef, NULL, 0); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst) +brw_inst::brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst) { init(opcode, exec_size, dst, NULL, 0); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, +brw_inst::brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, const brw_reg &src0) { const brw_reg src[1] = { src0 }; init(opcode, exec_size, dst, src, 1); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, +brw_inst::brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, const brw_reg &src0, const brw_reg &src1) { const brw_reg src[2] = { src0, src1 }; init(opcode, exec_size, dst, src, 2); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, +brw_inst::brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, const brw_reg &src2) { const brw_reg src[3] = { src0, src1, src2 }; init(opcode, exec_size, dst, src, 3); } -fs_inst::fs_inst(enum opcode opcode, uint8_t exec_width, const brw_reg &dst, +brw_inst::brw_inst(enum opcode opcode, uint8_t exec_width, const brw_reg &dst, const brw_reg src[], unsigned sources) { init(opcode, exec_width, dst, src, sources); } -fs_inst::fs_inst(const fs_inst &that) +brw_inst::brw_inst(const brw_inst &that) { memcpy((void*)this, &that, sizeof(that)); initialize_sources(this, that.src, that.sources); } -fs_inst::~fs_inst() +brw_inst::~brw_inst() { if (this->src != this->builtin_src) delete[] this->src; } static void -initialize_sources(fs_inst *inst, const brw_reg src[], uint8_t num_sources) +initialize_sources(brw_inst *inst, const brw_reg src[], uint8_t num_sources) { if (num_sources > ARRAY_SIZE(inst->builtin_src)) inst->src = new brw_reg[num_sources]; @@ -122,7 +122,7 @@ initialize_sources(fs_inst *inst, const brw_reg src[], uint8_t num_sources) } void -fs_inst::resize_sources(uint8_t num_sources) +brw_inst::resize_sources(uint8_t num_sources) { if (this->sources == num_sources) return; @@ -166,7 +166,7 @@ fs_inst::resize_sources(uint8_t num_sources) } bool -fs_inst::is_send_from_grf() const +brw_inst::is_send_from_grf() const { switch (opcode) { case SHADER_OPCODE_SEND: @@ -186,7 +186,7 @@ fs_inst::is_send_from_grf() const } bool -fs_inst::is_control_source(unsigned arg) const +brw_inst::is_control_source(unsigned arg) const { switch (opcode) { case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD: @@ -230,7 +230,7 @@ fs_inst::is_control_source(unsigned arg) const } bool -fs_inst::is_payload(unsigned arg) const +brw_inst::is_payload(unsigned arg) const { switch (opcode) { case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET: @@ -253,7 +253,7 @@ fs_inst::is_payload(unsigned arg) const } bool -fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const +brw_inst::can_do_source_mods(const struct intel_device_info *devinfo) const { if (is_send_from_grf()) return false; @@ -313,7 +313,7 @@ fs_inst::can_do_source_mods(const struct intel_device_info *devinfo) const } bool -fs_inst::can_do_cmod() const +brw_inst::can_do_cmod() const { switch (opcode) { case BRW_OPCODE_ADD: @@ -370,7 +370,7 @@ fs_inst::can_do_cmod() const } bool -fs_inst::can_change_types() const +brw_inst::can_change_types() const { return dst.type == src[0].type && !src[0].abs && !src[0].negate && !saturate && src[0].file != ATTR && @@ -391,7 +391,7 @@ fs_inst::can_change_types() const * it. */ bool -fs_inst::is_partial_write() const +brw_inst::is_partial_write() const { if (this->predicate && !this->predicate_trivial && this->opcode != BRW_OPCODE_SEL) @@ -407,7 +407,7 @@ fs_inst::is_partial_write() const } unsigned -fs_inst::components_read(unsigned i) const +brw_inst::components_read(unsigned i) const { /* Return zero if the source is not present. */ if (src[i].file == BAD_FILE) @@ -512,7 +512,7 @@ fs_inst::components_read(unsigned i) const } unsigned -fs_inst::size_read(const struct intel_device_info *devinfo, int arg) const +brw_inst::size_read(const struct intel_device_info *devinfo, int arg) const { switch (opcode) { case SHADER_OPCODE_SEND: @@ -637,7 +637,7 @@ namespace { } unsigned -fs_inst::flags_read(const intel_device_info *devinfo) const +brw_inst::flags_read(const intel_device_info *devinfo) const { if (devinfo->ver < 20 && (predicate == BRW_PREDICATE_ALIGN1_ANYV || predicate == BRW_PREDICATE_ALIGN1_ALLV)) { @@ -658,7 +658,7 @@ fs_inst::flags_read(const intel_device_info *devinfo) const } unsigned -fs_inst::flags_written(const intel_device_info *devinfo) const +brw_inst::flags_written(const intel_device_info *devinfo) const { if (conditional_mod && (opcode != BRW_OPCODE_SEL && opcode != BRW_OPCODE_CSEL && @@ -677,7 +677,7 @@ fs_inst::flags_written(const intel_device_info *devinfo) const } bool -fs_inst::has_sampler_residency() const +brw_inst::has_sampler_residency() const { switch (opcode) { case SHADER_OPCODE_TEX_LOGICAL: @@ -704,7 +704,7 @@ fs_inst::has_sampler_residency() const /* \sa inst_is_raw_move in brw_eu_validate. */ bool -fs_inst::is_raw_move() const +brw_inst::is_raw_move() const { if (opcode != BRW_OPCODE_MOV) return false; @@ -726,7 +726,7 @@ fs_inst::is_raw_move() const } bool -fs_inst::uses_address_register_implicitly() const +brw_inst::uses_address_register_implicitly() const { switch (opcode) { case SHADER_OPCODE_BROADCAST: @@ -739,7 +739,7 @@ fs_inst::uses_address_register_implicitly() const } bool -fs_inst::is_commutative() const +brw_inst::is_commutative() const { switch (opcode) { case BRW_OPCODE_AND: @@ -770,13 +770,13 @@ fs_inst::is_commutative() const } bool -fs_inst::is_3src(const struct brw_compiler *compiler) const +brw_inst::is_3src(const struct brw_compiler *compiler) const { return ::is_3src(&compiler->isa, opcode); } bool -fs_inst::is_math() const +brw_inst::is_math() const { return (opcode == SHADER_OPCODE_RCP || opcode == SHADER_OPCODE_RSQ || @@ -791,7 +791,7 @@ fs_inst::is_math() const } bool -fs_inst::is_control_flow_begin() const +brw_inst::is_control_flow_begin() const { switch (opcode) { case BRW_OPCODE_DO: @@ -804,7 +804,7 @@ fs_inst::is_control_flow_begin() const } bool -fs_inst::is_control_flow_end() const +brw_inst::is_control_flow_end() const { switch (opcode) { case BRW_OPCODE_ELSE: @@ -817,7 +817,7 @@ fs_inst::is_control_flow_end() const } bool -fs_inst::is_control_flow() const +brw_inst::is_control_flow() const { switch (opcode) { case BRW_OPCODE_DO: @@ -834,7 +834,7 @@ fs_inst::is_control_flow() const } bool -fs_inst::uses_indirect_addressing() const +brw_inst::uses_indirect_addressing() const { switch (opcode) { case SHADER_OPCODE_BROADCAST: @@ -847,7 +847,7 @@ fs_inst::uses_indirect_addressing() const } bool -fs_inst::can_do_saturate() const +brw_inst::can_do_saturate() const { switch (opcode) { case BRW_OPCODE_ADD: @@ -891,7 +891,7 @@ fs_inst::can_do_saturate() const } bool -fs_inst::reads_accumulator_implicitly() const +brw_inst::reads_accumulator_implicitly() const { switch (opcode) { case BRW_OPCODE_MAC: @@ -903,14 +903,14 @@ fs_inst::reads_accumulator_implicitly() const } bool -fs_inst::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const +brw_inst::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const { return writes_accumulator || (eot && intel_needs_workaround(devinfo, 14010017096)); } bool -fs_inst::has_side_effects() const +brw_inst::has_side_effects() const { switch (opcode) { case SHADER_OPCODE_SEND: @@ -938,7 +938,7 @@ fs_inst::has_side_effects() const } bool -fs_inst::is_volatile() const +brw_inst::is_volatile() const { return opcode == SHADER_OPCODE_MEMORY_LOAD_LOGICAL || ((opcode == SHADER_OPCODE_SEND || @@ -947,7 +947,7 @@ fs_inst::is_volatile() const #ifndef NDEBUG static bool -inst_is_in_block(const bblock_t *block, const fs_inst *inst) +inst_is_in_block(const bblock_t *block, const brw_inst *inst) { const exec_node *n = inst; @@ -974,7 +974,7 @@ adjust_later_block_ips(bblock_t *start_block, int ip_adjustment) } void -fs_inst::insert_after(bblock_t *block, fs_inst *inst) +brw_inst::insert_after(bblock_t *block, brw_inst *inst) { assert(this != inst); assert(block->end_ip_delta == 0); @@ -990,7 +990,7 @@ fs_inst::insert_after(bblock_t *block, fs_inst *inst) } void -fs_inst::insert_before(bblock_t *block, fs_inst *inst) +brw_inst::insert_before(bblock_t *block, brw_inst *inst) { assert(this != inst); assert(block->end_ip_delta == 0); @@ -1006,7 +1006,7 @@ fs_inst::insert_before(bblock_t *block, fs_inst *inst) } void -fs_inst::remove(bblock_t *block, bool defer_later_block_ip_updates) +brw_inst::remove(bblock_t *block, bool defer_later_block_ip_updates) { assert(inst_is_in_block(block, this) || !"Instruction not in block"); diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index 1fcf8a98645..d3621c754b0 100644 --- a/src/intel/compiler/brw_inst.h +++ b/src/intel/compiler/brw_inst.h @@ -39,29 +39,29 @@ struct bblock_t; -struct fs_inst : public exec_node { +struct brw_inst : public exec_node { private: - fs_inst &operator=(const fs_inst &); + brw_inst &operator=(const brw_inst &); void init(enum opcode opcode, uint8_t exec_width, const brw_reg &dst, const brw_reg *src, unsigned sources); public: - DECLARE_RALLOC_CXX_OPERATORS(fs_inst) + DECLARE_RALLOC_CXX_OPERATORS(brw_inst) - fs_inst(); - fs_inst(enum opcode opcode, uint8_t exec_size); - fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst); - fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, + brw_inst(); + brw_inst(enum opcode opcode, uint8_t exec_size); + brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst); + brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, const brw_reg &src0); - fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, + brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, const brw_reg &src0, const brw_reg &src1); - fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, + brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, const brw_reg &src0, const brw_reg &src1, const brw_reg &src2); - fs_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, + brw_inst(enum opcode opcode, uint8_t exec_size, const brw_reg &dst, const brw_reg src[], unsigned sources); - fs_inst(const fs_inst &that); - ~fs_inst(); + brw_inst(const brw_inst &that); + ~brw_inst(); void resize_sources(uint8_t num_sources); @@ -93,8 +93,8 @@ public: bool uses_indirect_addressing() const; void remove(bblock_t *block, bool defer_later_block_ip_updates = false); - void insert_after(bblock_t *block, fs_inst *inst); - void insert_before(bblock_t *block, fs_inst *inst); + void insert_after(bblock_t *block, brw_inst *inst); + void insert_before(bblock_t *block, brw_inst *inst); /** * True if the instruction has side effects other than writing to @@ -246,9 +246,9 @@ public: * Make the execution of \p inst dependent on the evaluation of a possibly * inverted predicate. */ -static inline fs_inst * +static inline brw_inst * set_predicate_inv(enum brw_predicate pred, bool inverse, - fs_inst *inst) + brw_inst *inst) { inst->predicate = pred; inst->predicate_inverse = inverse; @@ -258,8 +258,8 @@ set_predicate_inv(enum brw_predicate pred, bool inverse, /** * Make the execution of \p inst dependent on the evaluation of a predicate. */ -static inline fs_inst * -set_predicate(enum brw_predicate pred, fs_inst *inst) +static inline brw_inst * +set_predicate(enum brw_predicate pred, brw_inst *inst) { return set_predicate_inv(pred, false, inst); } @@ -268,8 +268,8 @@ set_predicate(enum brw_predicate pred, fs_inst *inst) * Write the result of evaluating the condition given by \p mod to a flag * register. */ -static inline fs_inst * -set_condmod(enum brw_conditional_mod mod, fs_inst *inst) +static inline brw_inst * +set_condmod(enum brw_conditional_mod mod, brw_inst *inst) { inst->conditional_mod = mod; return inst; @@ -279,8 +279,8 @@ set_condmod(enum brw_conditional_mod mod, fs_inst *inst) * Clamp the result of \p inst to the saturation range of its destination * datatype. */ -static inline fs_inst * -set_saturate(bool saturate, fs_inst *inst) +static inline brw_inst * +set_saturate(bool saturate, brw_inst *inst) { inst->saturate = saturate; return inst; @@ -293,7 +293,7 @@ set_saturate(bool saturate, fs_inst *inst) * UNIFORM and IMM files and 32B for all other files. */ inline unsigned -regs_written(const fs_inst *inst) +regs_written(const brw_inst *inst) { assert(inst->dst.file != UNIFORM && inst->dst.file != IMM); return DIV_ROUND_UP(reg_offset(inst->dst) % REG_SIZE + @@ -309,7 +309,7 @@ regs_written(const fs_inst *inst) * UNIFORM files and 32B for all other files. */ inline unsigned -regs_read(const struct intel_device_info *devinfo, const fs_inst *inst, unsigned i) +regs_read(const struct intel_device_info *devinfo, const brw_inst *inst, unsigned i) { if (inst->src[i].file == IMM) return 1; @@ -322,7 +322,7 @@ regs_read(const struct intel_device_info *devinfo, const fs_inst *inst, unsigned } static inline enum brw_reg_type -get_exec_type(const fs_inst *inst) +get_exec_type(const brw_inst *inst) { brw_reg_type exec_type = BRW_TYPE_B; @@ -368,13 +368,13 @@ get_exec_type(const fs_inst *inst) } static inline unsigned -get_exec_type_size(const fs_inst *inst) +get_exec_type_size(const brw_inst *inst) { return brw_type_size_bytes(get_exec_type(inst)); } static inline bool -is_send(const fs_inst *inst) +is_send(const brw_inst *inst) { return inst->mlen || inst->is_send_from_grf(); } @@ -384,7 +384,7 @@ is_send(const fs_inst *inst) * assumed to complete in-order. */ static inline bool -is_unordered(const intel_device_info *devinfo, const fs_inst *inst) +is_unordered(const intel_device_info *devinfo, const brw_inst *inst) { return is_send(inst) || (devinfo->ver < 20 && inst->is_math()) || inst->opcode == BRW_OPCODE_DPAS || @@ -408,7 +408,7 @@ is_unordered(const intel_device_info *devinfo, const fs_inst *inst) */ static inline bool has_dst_aligned_region_restriction(const intel_device_info *devinfo, - const fs_inst *inst, + const brw_inst *inst, brw_reg_type dst_type) { const brw_reg_type exec_type = get_exec_type(inst); @@ -436,7 +436,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo, static inline bool has_dst_aligned_region_restriction(const intel_device_info *devinfo, - const fs_inst *inst) + const brw_inst *inst) { return has_dst_aligned_region_restriction(devinfo, inst, inst->dst.type); } @@ -449,7 +449,7 @@ has_dst_aligned_region_restriction(const intel_device_info *devinfo, */ static inline bool has_subdword_integer_region_restriction(const intel_device_info *devinfo, - const fs_inst *inst, + const brw_inst *inst, const brw_reg *srcs, unsigned num_srcs) { if (devinfo->ver >= 20 && @@ -473,7 +473,7 @@ has_subdword_integer_region_restriction(const intel_device_info *devinfo, static inline bool has_subdword_integer_region_restriction(const intel_device_info *devinfo, - const fs_inst *inst) + const brw_inst *inst) { return has_subdword_integer_region_restriction(devinfo, inst, inst->src, inst->sources); @@ -490,7 +490,7 @@ has_subdword_integer_region_restriction(const intel_device_info *devinfo, */ inline bool is_copy_payload(const struct intel_device_info *devinfo, - brw_reg_file file, const fs_inst *inst) + brw_reg_file file, const brw_inst *inst) { if (inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD || inst->is_partial_write() || inst->saturate || @@ -520,7 +520,7 @@ is_copy_payload(const struct intel_device_info *devinfo, */ inline bool is_identity_payload(const struct intel_device_info *devinfo, - brw_reg_file file, const fs_inst *inst) + brw_reg_file file, const brw_inst *inst) { if (is_copy_payload(devinfo, file, inst)) { brw_reg reg = inst->src[0]; @@ -551,7 +551,7 @@ is_identity_payload(const struct intel_device_info *devinfo, */ inline bool is_multi_copy_payload(const struct intel_device_info *devinfo, - const fs_inst *inst) + const brw_inst *inst) { if (is_copy_payload(devinfo, VGRF, inst)) { for (unsigned i = 0; i < inst->sources; i++) { @@ -577,7 +577,7 @@ is_multi_copy_payload(const struct intel_device_info *devinfo, */ inline bool is_coalescing_payload(const struct intel_device_info *devinfo, - const brw::simple_allocator &alloc, const fs_inst *inst) + const brw::simple_allocator &alloc, const brw_inst *inst) { return is_identity_payload(devinfo, VGRF, inst) && inst->src[0].offset == 0 && @@ -585,14 +585,14 @@ is_coalescing_payload(const struct intel_device_info *devinfo, } bool -has_bank_conflict(const struct brw_isa_info *isa, const fs_inst *inst); +has_bank_conflict(const struct brw_isa_info *isa, const brw_inst *inst); /* Return the subset of flag registers that an instruction could * potentially read or write based on the execution controls and flag * subregister number of the instruction. */ static inline unsigned -brw_fs_flag_mask(const fs_inst *inst, unsigned width) +brw_fs_flag_mask(const brw_inst *inst, unsigned width) { assert(util_is_power_of_two_nonzero(width)); const unsigned start = (inst->flag_subreg * 16 + inst->group) & diff --git a/src/intel/compiler/brw_ir_performance.cpp b/src/intel/compiler/brw_ir_performance.cpp index d9816c64b56..a58fde81688 100644 --- a/src/intel/compiler/brw_ir_performance.cpp +++ b/src/intel/compiler/brw_ir_performance.cpp @@ -117,7 +117,7 @@ namespace { * instructions. */ struct instruction_info { - instruction_info(const struct brw_isa_info *isa, const fs_inst *inst) : + instruction_info(const struct brw_isa_info *isa, const brw_inst *inst) : isa(isa), devinfo(isa->devinfo), op(inst->opcode), td(inst->dst.type), sd(DIV_ROUND_UP(inst->size_written, REG_SIZE)), tx(get_exec_type(inst)), sx(0), ss(0), @@ -863,7 +863,7 @@ namespace { */ unsigned accum_reg_of_channel(const intel_device_info *devinfo, - const fs_inst *inst, + const brw_inst *inst, brw_reg_type tx, unsigned i) { assert(inst->reads_accumulator_implicitly() || @@ -878,7 +878,7 @@ namespace { */ void issue_inst(state &st, const struct brw_isa_info *isa, - const fs_inst *inst) + const brw_inst *inst) { const struct intel_device_info *devinfo = isa->devinfo; const instruction_info info(isa, inst); @@ -1038,7 +1038,7 @@ namespace { foreach_block(block, s->cfg) { const unsigned elapsed0 = elapsed; - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(brw_inst, inst, block) { const unsigned clock0 = st.unit_ready[EU_UNIT_FE]; issue_inst(st, &s->compiler->isa, inst); diff --git a/src/intel/compiler/brw_lower.cpp b/src/intel/compiler/brw_lower.cpp index e8ce42de325..1e8600c6ad1 100644 --- a/src/intel/compiler/brw_lower.cpp +++ b/src/intel/compiler/brw_lower.cpp @@ -33,7 +33,7 @@ brw_lower_scalar_fp64_MAD(fs_visitor &s) if (devinfo->ver != 9) return false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode == BRW_OPCODE_MAD && inst->dst.type == BRW_TYPE_DF) { for (unsigned i = 0; i < 3; i++) { @@ -54,7 +54,7 @@ brw_lower_load_payload(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe (block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe (block, brw_inst, inst, s.cfg) { if (inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) continue; @@ -111,7 +111,7 @@ brw_lower_csel(fs_visitor &s) const intel_device_info *devinfo = s.devinfo; bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode != BRW_OPCODE_CSEL) continue; @@ -186,7 +186,7 @@ brw_lower_sub_sat(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { const brw_builder ibld(&s, block, inst); if (inst->opcode == SHADER_OPCODE_USUB_SAT || @@ -224,14 +224,14 @@ brw_lower_sub_sat(fs_visitor &s) inst->src[1].type); ibld.MOV(acc, inst->src[1]); - fs_inst *add = ibld.ADD(inst->dst, acc, inst->src[0]); + brw_inst *add = ibld.ADD(inst->dst, acc, inst->src[0]); add->saturate = true; add->src[0].negate = true; } else if (inst->opcode == SHADER_OPCODE_ISUB_SAT) { /* tmp = src1 >> 1; * dst = add.sat(add.sat(src0, -tmp), -(src1 - tmp)); */ - fs_inst *add; + brw_inst *add; brw_reg tmp = ibld.vgrf(inst->src[0].type); ibld.SHR(tmp, inst->src[1], brw_imm_d(1)); @@ -247,7 +247,7 @@ brw_lower_sub_sat(fs_visitor &s) ibld.CMP(ibld.null_reg_d(), inst->src[0], inst->src[1], BRW_CONDITIONAL_G); - fs_inst *add = ibld.ADD(inst->dst, inst->src[0], inst->src[1]); + brw_inst *add = ibld.ADD(inst->dst, inst->src[0], inst->src[1]); add->src[1].negate = !add->src[1].negate; ibld.SEL(inst->dst, inst->dst, brw_imm_ud(0)) @@ -291,7 +291,7 @@ brw_lower_barycentrics(fs_visitor &s) bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->exec_size < 16) continue; @@ -322,7 +322,7 @@ brw_lower_barycentrics(fs_visitor &s) for (unsigned i = 0; i < 2; i++) { for (unsigned g = 0; g < inst->exec_size / 8; g++) { - fs_inst *mov = ibld.at(block, inst->next).group(8, g) + brw_inst *mov = ibld.at(block, inst->next).group(8, g) .MOV(horiz_offset(offset(inst->dst, ibld, i), 8 * g), offset(tmp, ubld, 2 * g + i)); @@ -352,7 +352,7 @@ brw_lower_barycentrics(fs_visitor &s) * swizzles of the source, specified as \p swz0 and \p swz1. */ static bool -lower_derivative(fs_visitor &s, bblock_t *block, fs_inst *inst, +lower_derivative(fs_visitor &s, bblock_t *block, brw_inst *inst, unsigned swz0, unsigned swz1) { const brw_builder ubld = brw_builder(&s, block, inst).exec_all(); @@ -382,7 +382,7 @@ brw_lower_derivatives(fs_visitor &s) if (s.devinfo->verx10 < 125) return false; - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { if (inst->opcode == FS_OPCODE_DDX_COARSE) progress |= lower_derivative(s, block, inst, BRW_SWIZZLE_XXXX, BRW_SWIZZLE_YYYY); @@ -418,7 +418,7 @@ brw_lower_find_live_channel(fs_visitor &s) s.stage == MESA_SHADER_FRAGMENT && brw_wm_prog_data(s.prog_data)->uses_vmask; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode != SHADER_OPCODE_FIND_LIVE_CHANNEL && inst->opcode != SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL && inst->opcode != SHADER_OPCODE_LOAD_LIVE_CHANNELS) @@ -516,7 +516,7 @@ brw_lower_sends_overlapping_payload(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe (block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe (block, brw_inst, inst, s.cfg) { if (inst->opcode == SHADER_OPCODE_SEND && inst->ex_mlen > 0 && regions_overlap(inst->src[2], inst->mlen * REG_SIZE, inst->src[3], inst->ex_mlen * REG_SIZE)) { @@ -562,7 +562,7 @@ brw_lower_3src_null_dest(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe (block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe (block, brw_inst, inst, s.cfg) { if (inst->is_3src(s.compiler) && inst->dst.is_null()) { inst->dst = brw_vgrf(s.alloc.allocate(s.dispatch_width / 8), inst->dst.type); @@ -598,7 +598,7 @@ brw_lower_alu_restrictions(fs_visitor &s) const intel_device_info *devinfo = s.devinfo; bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { switch (inst->opcode) { case BRW_OPCODE_MOV: if (unsupported_64bit_type(devinfo, inst->dst.type)) { @@ -665,7 +665,7 @@ brw_lower_alu_restrictions(fs_visitor &s) } static void -brw_lower_vgrf_to_fixed_grf(const struct intel_device_info *devinfo, fs_inst *inst, +brw_lower_vgrf_to_fixed_grf(const struct intel_device_info *devinfo, brw_inst *inst, brw_reg *reg, bool compressed) { if (reg->file != VGRF) @@ -729,7 +729,7 @@ brw_lower_vgrfs_to_fixed_grfs(fs_visitor &s) { assert(s.grf_used || !"Must be called after register allocation"); - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { /* If the instruction writes to more than one register, it needs to be * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the * hardware figures out by itself what the right compression mode is, @@ -774,7 +774,7 @@ brw_s0(enum brw_reg_type type, unsigned subnr) } static bool -brw_lower_send_gather_inst(fs_visitor &s, bblock_t *block, fs_inst *inst) +brw_lower_send_gather_inst(fs_visitor &s, bblock_t *block, brw_inst *inst) { const intel_device_info *devinfo = s.devinfo; assert(devinfo->ver >= 30); @@ -831,7 +831,7 @@ brw_lower_send_gather(fs_visitor &s) bool progress = false; - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { if (inst->opcode == SHADER_OPCODE_SEND_GATHER) progress |= brw_lower_send_gather_inst(s, block, inst); } @@ -848,7 +848,7 @@ brw_lower_load_subgroup_invocation(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode != SHADER_OPCODE_LOAD_SUBGROUP_INVOCATION) continue; @@ -890,7 +890,7 @@ brw_lower_indirect_mov(fs_visitor &s) if (s.devinfo->ver < 20) return progress; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode == SHADER_OPCODE_MOV_INDIRECT) { if (brw_type_size_bytes(inst->src[0].type) > 1 && brw_type_size_bytes(inst->dst.type) > 1) { diff --git a/src/intel/compiler/brw_lower_dpas.cpp b/src/intel/compiler/brw_lower_dpas.cpp index 0a247f6f573..f098764a1c4 100644 --- a/src/intel/compiler/brw_lower_dpas.cpp +++ b/src/intel/compiler/brw_lower_dpas.cpp @@ -9,7 +9,7 @@ using namespace brw; static void -f16_using_mac(const brw_builder &bld, fs_inst *inst) +f16_using_mac(const brw_builder &bld, brw_inst *inst) { /* We only intend to support configurations where the destination and * accumulator have the same type. @@ -115,7 +115,7 @@ f16_using_mac(const brw_builder &bld, fs_inst *inst) } static void -int8_using_dp4a(const brw_builder &bld, fs_inst *inst) +int8_using_dp4a(const brw_builder &bld, brw_inst *inst) { /* We only intend to support configurations where the destination and * accumulator have the same type. @@ -162,7 +162,7 @@ int8_using_dp4a(const brw_builder &bld, fs_inst *inst) } static void -int8_using_mul_add(const brw_builder &bld, fs_inst *inst) +int8_using_mul_add(const brw_builder &bld, brw_inst *inst) { /* We only intend to support configurations where the destination and * accumulator have the same type. @@ -275,7 +275,7 @@ brw_lower_dpas(fs_visitor &v) { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, v.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, v.cfg) { if (inst->opcode != BRW_OPCODE_DPAS) continue; diff --git a/src/intel/compiler/brw_lower_integer_multiplication.cpp b/src/intel/compiler/brw_lower_integer_multiplication.cpp index c16ba89edbb..88259cdaa31 100644 --- a/src/intel/compiler/brw_lower_integer_multiplication.cpp +++ b/src/intel/compiler/brw_lower_integer_multiplication.cpp @@ -139,7 +139,7 @@ factor_uint32(uint32_t x, unsigned *result_a, unsigned *result_b) } static void -brw_lower_mul_dword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) +brw_lower_mul_dword_inst(fs_visitor &s, brw_inst *inst, bblock_t *block) { const intel_device_info *devinfo = s.devinfo; const brw_builder ibld(&s, block, inst); @@ -301,7 +301,7 @@ brw_lower_mul_dword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) } static void -brw_lower_mul_qword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) +brw_lower_mul_qword_inst(fs_visitor &s, brw_inst *inst, bblock_t *block) { const intel_device_info *devinfo = s.devinfo; const brw_builder ibld(&s, block, inst); @@ -334,7 +334,7 @@ brw_lower_mul_qword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) brw_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), BRW_TYPE_UD), inst->group % acc_width); - fs_inst *mul = ibld.MUL(acc, + brw_inst *mul = ibld.MUL(acc, subscript(inst->src[0], BRW_TYPE_UD, 0), subscript(inst->src[1], BRW_TYPE_UW, 0)); mul->writes_accumulator = true; @@ -370,7 +370,7 @@ brw_lower_mul_qword_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) } static void -brw_lower_mulh_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) +brw_lower_mulh_inst(fs_visitor &s, brw_inst *inst, bblock_t *block) { const intel_device_info *devinfo = s.devinfo; const brw_builder ibld(&s, block, inst); @@ -392,7 +392,7 @@ brw_lower_mulh_inst(fs_visitor &s, fs_inst *inst, bblock_t *block) const unsigned acc_width = reg_unit(devinfo) * 8; const brw_reg acc = suboffset(retype(brw_acc_reg(inst->exec_size), inst->dst.type), inst->group % acc_width); - fs_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]); + brw_inst *mul = ibld.MUL(acc, inst->src[0], inst->src[1]); ibld.MACH(inst->dst, inst->src[0], inst->src[1]); /* Until Gfx8, integer multiplies read 32-bits from one source, @@ -419,7 +419,7 @@ brw_lower_integer_multiplication(fs_visitor &s) const intel_device_info *devinfo = s.devinfo; bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode == BRW_OPCODE_MUL) { /* If the instruction is already in a form that does not need lowering, * return early. diff --git a/src/intel/compiler/brw_lower_logical_sends.cpp b/src/intel/compiler/brw_lower_logical_sends.cpp index c2b0c461bc5..9838a059548 100644 --- a/src/intel/compiler/brw_lower_logical_sends.cpp +++ b/src/intel/compiler/brw_lower_logical_sends.cpp @@ -32,7 +32,7 @@ using namespace brw; static void -lower_urb_read_logical_send(const brw_builder &bld, fs_inst *inst) +lower_urb_read_logical_send(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const bool per_slot_present = @@ -75,7 +75,7 @@ lower_urb_read_logical_send(const brw_builder &bld, fs_inst *inst) } static void -lower_urb_read_logical_send_xe2(const brw_builder &bld, fs_inst *inst) +lower_urb_read_logical_send_xe2(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); @@ -134,7 +134,7 @@ lower_urb_read_logical_send_xe2(const brw_builder &bld, fs_inst *inst) } static void -lower_urb_write_logical_send(const brw_builder &bld, fs_inst *inst) +lower_urb_write_logical_send(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const bool per_slot_present = @@ -191,7 +191,7 @@ lower_urb_write_logical_send(const brw_builder &bld, fs_inst *inst) } static void -lower_urb_write_logical_send_xe2(const brw_builder &bld, fs_inst *inst) +lower_urb_write_logical_send_xe2(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); @@ -283,7 +283,7 @@ setup_color_payload(const brw_builder &bld, const brw_wm_prog_key *key, } static void -lower_fb_write_logical_send(const brw_builder &bld, fs_inst *inst, +lower_fb_write_logical_send(const brw_builder &bld, brw_inst *inst, const struct brw_wm_prog_data *prog_data, const brw_wm_prog_key *key, const fs_thread_payload &fs_payload) @@ -457,7 +457,7 @@ lower_fb_write_logical_send(const brw_builder &bld, fs_inst *inst, /* Send from the GRF */ brw_reg payload = brw_vgrf(-1, BRW_TYPE_F); - fs_inst *load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size); + brw_inst *load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size); payload.nr = bld.shader->alloc.allocate(regs_written(load)); load->dst = payload; @@ -513,7 +513,7 @@ lower_fb_write_logical_send(const brw_builder &bld, fs_inst *inst, } static void -lower_fb_read_logical_send(const brw_builder &bld, fs_inst *inst, +lower_fb_read_logical_send(const brw_builder &bld, brw_inst *inst, const struct brw_wm_prog_data *wm_prog_data) { const intel_device_info *devinfo = bld.shader->devinfo; @@ -675,7 +675,7 @@ sampler_msg_type(const intel_device_info *devinfo, * Emit a LOAD_PAYLOAD instruction while ensuring the sources are aligned to * the given requested_alignment_sz. */ -static fs_inst * +static brw_inst * emit_load_payload_with_padding(const brw_builder &bld, const brw_reg &dst, const brw_reg *src, unsigned sources, unsigned header_size, @@ -707,7 +707,7 @@ emit_load_payload_with_padding(const brw_builder &bld, const brw_reg &dst, } } - fs_inst *inst = bld.LOAD_PAYLOAD(dst, src_comps, length, header_size); + brw_inst *inst = bld.LOAD_PAYLOAD(dst, src_comps, length, header_size); delete[] src_comps; return inst; @@ -734,7 +734,7 @@ shader_opcode_needs_header(opcode op) } static void -lower_sampler_logical_send(const brw_builder &bld, fs_inst *inst, +lower_sampler_logical_send(const brw_builder &bld, brw_inst *inst, const brw_reg &coordinate, const brw_reg &shadow_c, brw_reg lod, const brw_reg &lod2, @@ -1102,7 +1102,7 @@ lower_sampler_logical_send(const brw_builder &bld, fs_inst *inst, * elements. In SIMD8H case hardware simply expects the components to be * padded (i.e., aligned on reg boundary). */ - fs_inst *load_payload_inst = + brw_inst *load_payload_inst = emit_load_payload_with_padding(bld, src_payload, sources, length, header_size, REG_SIZE * reg_unit(devinfo)); unsigned mlen = load_payload_inst->size_written / REG_SIZE; @@ -1209,7 +1209,7 @@ lower_sampler_logical_send(const brw_builder &bld, fs_inst *inst, static unsigned get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, - const fs_inst *inst) + const brw_inst *inst) { assert(inst); const brw_reg *src = inst->src; @@ -1260,7 +1260,7 @@ get_sampler_msg_payload_type_bit_size(const intel_device_info *devinfo, } static void -lower_sampler_logical_send(const brw_builder &bld, fs_inst *inst) +lower_sampler_logical_send(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const brw_reg coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE]; @@ -1303,7 +1303,7 @@ lower_sampler_logical_send(const brw_builder &bld, fs_inst *inst) * Predicate the specified instruction on the vector mask. */ static void -emit_predicate_on_vector_mask(const brw_builder &bld, fs_inst *inst) +emit_predicate_on_vector_mask(const brw_builder &bld, brw_inst *inst) { assert(bld.shader->stage == MESA_SHADER_FRAGMENT && bld.group() == inst->group && @@ -1337,7 +1337,7 @@ emit_predicate_on_vector_mask(const brw_builder &bld, fs_inst *inst) } static void -setup_surface_descriptors(const brw_builder &bld, fs_inst *inst, uint32_t desc, +setup_surface_descriptors(const brw_builder &bld, brw_inst *inst, uint32_t desc, const brw_reg &surface, const brw_reg &surface_handle) { const brw_compiler *compiler = bld.shader->compiler; @@ -1370,7 +1370,7 @@ setup_surface_descriptors(const brw_builder &bld, fs_inst *inst, uint32_t desc, } static void -setup_lsc_surface_descriptors(const brw_builder &bld, fs_inst *inst, +setup_lsc_surface_descriptors(const brw_builder &bld, brw_inst *inst, uint32_t desc, const brw_reg &surface) { const ASSERTED intel_device_info *devinfo = bld.shader->devinfo; @@ -1427,7 +1427,7 @@ lsc_addr_size_for_type(enum brw_reg_type type) } static void -lower_lsc_memory_logical_send(const brw_builder &bld, fs_inst *inst) +lower_lsc_memory_logical_send(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; assert(devinfo->has_lsc); @@ -1615,7 +1615,7 @@ emit_a64_oword_block_header(const brw_builder &bld, const brw_reg &addr) } static void -lower_hdc_memory_logical_send(const brw_builder &bld, fs_inst *inst) +lower_hdc_memory_logical_send(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const brw_compiler *compiler = bld.shader->compiler; @@ -1743,7 +1743,7 @@ lower_hdc_memory_logical_send(const brw_builder &bld, fs_inst *inst) lsc_data_size_bytes(data_size) / 4); payload = bld.vgrf(BRW_TYPE_UD, payload_size_UDs); - fs_inst *load_payload = + brw_inst *load_payload = emit_load_payload_with_padding(bld, payload, data, num_sources, header.file != BAD_FILE ? 1 : 0, REG_SIZE); @@ -1907,7 +1907,7 @@ lower_hdc_memory_logical_send(const brw_builder &bld, fs_inst *inst) static void lower_lsc_varying_pull_constant_logical_send(const brw_builder &bld, - fs_inst *inst) + brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; ASSERTED const brw_compiler *compiler = bld.shader->compiler; @@ -1993,7 +1993,7 @@ lower_lsc_varying_pull_constant_logical_send(const brw_builder &bld, } static void -lower_varying_pull_constant_logical_send(const brw_builder &bld, fs_inst *inst) +lower_varying_pull_constant_logical_send(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; const brw_compiler *compiler = bld.shader->compiler; @@ -2071,7 +2071,7 @@ lower_varying_pull_constant_logical_send(const brw_builder &bld, fs_inst *inst) } static void -lower_interpolator_logical_send(const brw_builder &bld, fs_inst *inst, +lower_interpolator_logical_send(const brw_builder &bld, brw_inst *inst, const struct brw_wm_prog_key *wm_prog_key, const struct brw_wm_prog_data *wm_prog_data) { @@ -2195,7 +2195,7 @@ lower_interpolator_logical_send(const brw_builder &bld, fs_inst *inst, } static void -lower_btd_logical_send(const brw_builder &bld, fs_inst *inst) +lower_btd_logical_send(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; brw_reg global_addr = inst->src[0]; @@ -2275,7 +2275,7 @@ lower_btd_logical_send(const brw_builder &bld, fs_inst *inst) } static void -lower_trace_ray_logical_send(const brw_builder &bld, fs_inst *inst) +lower_trace_ray_logical_send(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; /* The emit_uniformize() in brw_fs_nir.cpp will generate an horizontal @@ -2372,7 +2372,7 @@ lower_trace_ray_logical_send(const brw_builder &bld, fs_inst *inst) } static void -lower_get_buffer_size(const brw_builder &bld, fs_inst *inst) +lower_get_buffer_size(const brw_builder &bld, brw_inst *inst) { const intel_device_info *devinfo = bld.shader->devinfo; /* Since we can only execute this instruction on uniform bti/surface @@ -2411,7 +2411,7 @@ brw_lower_logical_sends(fs_visitor &s) const intel_device_info *devinfo = s.devinfo; bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { const brw_builder ibld(&s, block, inst); switch (inst->opcode) { @@ -2538,7 +2538,7 @@ brw_lower_uniform_pull_constant_loads(fs_visitor &s) const intel_device_info *devinfo = s.devinfo; bool progress = false; - foreach_block_and_inst (block, fs_inst, inst, s.cfg) { + foreach_block_and_inst (block, brw_inst, inst, s.cfg) { if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD) continue; @@ -2628,7 +2628,7 @@ brw_lower_send_descriptors(fs_visitor &s) const intel_device_info *devinfo = s.devinfo; bool progress = false; - foreach_block_and_inst (block, fs_inst, inst, s.cfg) { + foreach_block_and_inst (block, brw_inst, inst, s.cfg) { if (inst->opcode != SHADER_OPCODE_SEND && inst->opcode != SHADER_OPCODE_SEND_GATHER) continue; diff --git a/src/intel/compiler/brw_lower_pack.cpp b/src/intel/compiler/brw_lower_pack.cpp index 805046f323f..5f4ec027599 100644 --- a/src/intel/compiler/brw_lower_pack.cpp +++ b/src/intel/compiler/brw_lower_pack.cpp @@ -33,7 +33,7 @@ brw_lower_pack(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode != FS_OPCODE_PACK && inst->opcode != FS_OPCODE_PACK_HALF_2x16_SPLIT) continue; diff --git a/src/intel/compiler/brw_lower_regioning.cpp b/src/intel/compiler/brw_lower_regioning.cpp index 26f6ffc5b23..ceb3e65e661 100644 --- a/src/intel/compiler/brw_lower_regioning.cpp +++ b/src/intel/compiler/brw_lower_regioning.cpp @@ -36,7 +36,7 @@ namespace { * using raw move." */ bool - is_byte_raw_mov(const fs_inst *inst) + is_byte_raw_mov(const brw_inst *inst) { return brw_type_size_bytes(inst->dst.type) == 1 && inst->opcode == BRW_OPCODE_MOV && @@ -51,7 +51,7 @@ namespace { * instruction affected by a regioning restriction. */ unsigned - required_src_byte_stride(const intel_device_info *devinfo, const fs_inst *inst, + required_src_byte_stride(const intel_device_info *devinfo, const brw_inst *inst, unsigned i) { if (has_dst_aligned_region_restriction(devinfo, inst)) { @@ -78,7 +78,7 @@ namespace { * of an instruction affected by a regioning restriction. */ unsigned - required_src_byte_offset(const intel_device_info *devinfo, const fs_inst *inst, + required_src_byte_offset(const intel_device_info *devinfo, const brw_inst *inst, unsigned i) { if (has_dst_aligned_region_restriction(devinfo, inst)) { @@ -145,7 +145,7 @@ namespace { * that requires it to have some particular alignment. */ unsigned - required_dst_byte_stride(const fs_inst *inst) + required_dst_byte_stride(const brw_inst *inst) { if (inst->dst.is_accumulator()) { /* If the destination is an accumulator, insist that we leave the @@ -201,7 +201,7 @@ namespace { * the sources. */ unsigned - required_dst_byte_offset(const intel_device_info *devinfo, const fs_inst *inst) + required_dst_byte_offset(const intel_device_info *devinfo, const brw_inst *inst) { for (unsigned i = 0; i < inst->sources; i++) { if (!is_uniform(inst->src[i]) && !inst->is_control_source(i)) @@ -218,7 +218,7 @@ namespace { * the specified platform. */ brw_reg_type - required_exec_type(const intel_device_info *devinfo, const fs_inst *inst) + required_exec_type(const intel_device_info *devinfo, const brw_inst *inst) { const brw_reg_type t = get_exec_type(inst); const bool has_64bit = brw_type_is_float(t) ? @@ -294,7 +294,7 @@ namespace { * specified for the i-th source region. */ bool - has_invalid_src_region(const intel_device_info *devinfo, const fs_inst *inst, + has_invalid_src_region(const intel_device_info *devinfo, const brw_inst *inst, unsigned i) { /* Wa_22016140776: @@ -331,7 +331,7 @@ namespace { */ bool has_invalid_dst_region(const intel_device_info *devinfo, - const fs_inst *inst) + const brw_inst *inst) { if (is_send(inst)) { return false; @@ -356,7 +356,7 @@ namespace { * source or destination modifiers into separate MOV instructions. */ unsigned - has_invalid_exec_type(const intel_device_info *devinfo, const fs_inst *inst) + has_invalid_exec_type(const intel_device_info *devinfo, const brw_inst *inst) { if (required_exec_type(devinfo, inst) != get_exec_type(inst)) { switch (inst->opcode) { @@ -384,7 +384,7 @@ namespace { */ bool has_invalid_src_conversion(const intel_device_info *devinfo, - const fs_inst *inst) + const brw_inst *inst) { /* Scalar byte to float conversion is not allowed on DG2+ */ return devinfo->verx10 >= 125 && @@ -400,7 +400,7 @@ namespace { */ bool has_invalid_src_modifiers(const intel_device_info *devinfo, - const fs_inst *inst, unsigned i) + const brw_inst *inst, unsigned i) { return (!inst->can_do_source_mods(devinfo) && (inst->src[i].negate || inst->src[i].abs)) || @@ -415,7 +415,7 @@ namespace { * specified for the destination. */ bool - has_invalid_conversion(const intel_device_info *devinfo, const fs_inst *inst) + has_invalid_conversion(const intel_device_info *devinfo, const brw_inst *inst) { switch (inst->opcode) { case BRW_OPCODE_MOV: @@ -436,7 +436,7 @@ namespace { * Return whether the instruction has unsupported destination modifiers. */ bool - has_invalid_dst_modifiers(const intel_device_info *devinfo, const fs_inst *inst) + has_invalid_dst_modifiers(const intel_device_info *devinfo, const brw_inst *inst) { return (has_invalid_exec_type(devinfo, inst) && (inst->saturate || inst->conditional_mod)) || @@ -449,7 +449,7 @@ namespace { * the comparison result. */ bool - has_inconsistent_cmod(const fs_inst *inst) + has_inconsistent_cmod(const brw_inst *inst) { return inst->opcode == BRW_OPCODE_SEL || inst->opcode == BRW_OPCODE_CSEL || @@ -458,7 +458,7 @@ namespace { } bool - lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst); + lower_instruction(fs_visitor *v, bblock_t *block, brw_inst *inst); } /** @@ -468,7 +468,7 @@ namespace { * MOV instruction prior to the original instruction. */ bool -brw_lower_src_modifiers(fs_visitor &s, bblock_t *block, fs_inst *inst, unsigned i) +brw_lower_src_modifiers(fs_visitor &s, bblock_t *block, brw_inst *inst, unsigned i) { assert(inst->components_read(i) == 1); assert(s.devinfo->has_integer_dword_mul || @@ -495,7 +495,7 @@ namespace { * instruction. */ bool - lower_dst_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_dst_modifiers(fs_visitor *v, bblock_t *block, brw_inst *inst) { const brw_builder ibld(v, block, inst); const brw_reg_type type = get_exec_type(inst); @@ -513,7 +513,7 @@ namespace { tmp = horiz_stride(tmp, stride); /* Emit a MOV taking care of all the destination modifiers. */ - fs_inst *mov = ibld.at(block, inst->next).MOV(inst->dst, tmp); + brw_inst *mov = ibld.at(block, inst->next).MOV(inst->dst, tmp); mov->saturate = inst->saturate; if (!has_inconsistent_cmod(inst)) mov->conditional_mod = inst->conditional_mod; @@ -544,7 +544,7 @@ namespace { * copies into a temporary with the same channel layout as the destination. */ bool - lower_src_region(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i) + lower_src_region(fs_visitor *v, bblock_t *block, brw_inst *inst, unsigned i) { assert(inst->components_read(i) == 1); const intel_device_info *devinfo = v->devinfo; @@ -578,7 +578,7 @@ namespace { raw_src.abs = false; for (unsigned j = 0; j < n; j++) { - fs_inst *jnst = ibld.MOV(subscript(tmp, raw_type, j), + brw_inst *jnst = ibld.MOV(subscript(tmp, raw_type, j), subscript(raw_src, raw_type, j)); if (has_subdword_integer_region_restriction(devinfo, jnst)) { /* The copy isn't guaranteed to comply with all subdword integer @@ -606,7 +606,7 @@ namespace { * sources. */ bool - lower_dst_region(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_dst_region(fs_visitor *v, bblock_t *block, brw_inst *inst) { /* We cannot replace the result of an integer multiply which writes the * accumulator because MUL+MACH pairs act on the accumulator as a 66-bit @@ -647,7 +647,7 @@ namespace { } for (unsigned j = 0; j < n; j++) { - fs_inst *jnst = ibld.at(block, inst->next).MOV(subscript(inst->dst, raw_type, j), + brw_inst *jnst = ibld.at(block, inst->next).MOV(subscript(inst->dst, raw_type, j), subscript(tmp, raw_type, j)); if (has_subdword_integer_region_restriction(v->devinfo, jnst)) { /* The copy isn't guaranteed to comply with all subdword integer @@ -681,7 +681,7 @@ namespace { * where the execution type of an instruction is unsupported. */ bool - lower_exec_type(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_exec_type(fs_visitor *v, bblock_t *block, brw_inst *inst) { assert(inst->dst.type == get_exec_type(inst)); const unsigned mask = has_invalid_exec_type(v->devinfo, inst); @@ -694,7 +694,7 @@ namespace { tmp = horiz_stride(tmp, inst->dst.stride); for (unsigned j = 0; j < n; j++) { - fs_inst sub_inst = *inst; + brw_inst sub_inst = *inst; for (unsigned i = 0; i < inst->sources; i++) { if (mask & (1u << i)) { @@ -709,7 +709,7 @@ namespace { assert(!sub_inst.flags_written(v->devinfo) && !sub_inst.saturate); ibld.emit(sub_inst); - fs_inst *mov = ibld.MOV(subscript(inst->dst, raw_type, j), + brw_inst *mov = ibld.MOV(subscript(inst->dst, raw_type, j), subscript(tmp, raw_type, j)); if (inst->opcode != BRW_OPCODE_SEL) { mov->predicate = inst->predicate; @@ -731,7 +731,7 @@ namespace { * the general lowering in lower_src_modifiers or lower_src_region. */ void - lower_src_conversion(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_src_conversion(fs_visitor *v, bblock_t *block, brw_inst *inst) { const intel_device_info *devinfo = v->devinfo; const brw_builder ibld = brw_builder(v, block, inst).scalar_group(); @@ -740,7 +740,7 @@ namespace { assert(is_uniform(inst->src[0])); brw_reg tmp = ibld.vgrf(brw_type_with_size(inst->src[0].type, 32)); - fs_inst *mov = ibld.MOV(tmp, inst->src[0]); + brw_inst *mov = ibld.MOV(tmp, inst->src[0]); inst->src[0] = component(tmp, 0); @@ -760,7 +760,7 @@ namespace { * instruction. */ bool - lower_instruction(fs_visitor *v, bblock_t *block, fs_inst *inst) + lower_instruction(fs_visitor *v, bblock_t *block, brw_inst *inst) { const intel_device_info *devinfo = v->devinfo; bool progress = false; @@ -805,7 +805,7 @@ brw_lower_regioning(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) progress |= lower_instruction(&s, block, inst); if (progress) diff --git a/src/intel/compiler/brw_lower_scoreboard.cpp b/src/intel/compiler/brw_lower_scoreboard.cpp index 83415fc14d0..6852fe1e7c9 100644 --- a/src/intel/compiler/brw_lower_scoreboard.cpp +++ b/src/intel/compiler/brw_lower_scoreboard.cpp @@ -72,7 +72,7 @@ namespace { * instruction (e.g. when TGL_PIPE_NONE is specified in tgl_swsb). */ tgl_pipe - inferred_sync_pipe(const struct intel_device_info *devinfo, const fs_inst *inst) + inferred_sync_pipe(const struct intel_device_info *devinfo, const brw_inst *inst) { if (devinfo->verx10 >= 125) { bool has_int_src = false, has_long_src = false; @@ -115,7 +115,7 @@ namespace { * RegDist synchronization mechanism. */ tgl_pipe - inferred_exec_pipe(const struct intel_device_info *devinfo, const fs_inst *inst) + inferred_exec_pipe(const struct intel_device_info *devinfo, const brw_inst *inst) { const brw_reg_type t = get_exec_type(inst); const bool is_dword_multiply = !brw_type_is_float(t) && @@ -178,7 +178,7 @@ namespace { * instruction. */ unsigned - ordered_unit(const struct intel_device_info *devinfo, const fs_inst *inst, + ordered_unit(const struct intel_device_info *devinfo, const brw_inst *inst, unsigned p) { switch (inst->opcode) { @@ -278,7 +278,7 @@ namespace { ordered_address jp(TGL_PIPE_ALL, 0); unsigned ip = 0; - foreach_block_and_inst(block, fs_inst, inst, shader->cfg) { + foreach_block_and_inst(block, brw_inst, inst, shader->cfg) { jps[ip] = jp; for (unsigned p = 0; p < IDX(TGL_PIPE_ALL); p++) jp.jp[p] += ordered_unit(shader->devinfo, inst, p); @@ -648,7 +648,7 @@ namespace { */ dependency dependency_for_write(const struct intel_device_info *devinfo, - const fs_inst *inst, dependency dep) + const brw_inst *inst, dependency dep) { if (!is_unordered(devinfo, inst) && is_single_pipe(dep.jp, inferred_exec_pipe(devinfo, inst))) @@ -966,7 +966,7 @@ namespace { */ tgl_sbid_mode baked_unordered_dependency_mode(const struct intel_device_info *devinfo, - const fs_inst *inst, + const brw_inst *inst, const dependency_list &deps, const ordered_address &jp) { @@ -997,7 +997,7 @@ namespace { */ bool baked_ordered_dependency_mode(const struct intel_device_info *devinfo, - const fs_inst *inst, + const brw_inst *inst, const dependency_list &deps, const ordered_address &jp) { @@ -1043,7 +1043,7 @@ namespace { */ void update_inst_scoreboard(const fs_visitor *shader, const ordered_address *jps, - const fs_inst *inst, unsigned ip, scoreboard &sb) + const brw_inst *inst, unsigned ip, scoreboard &sb) { const bool exec_all = inst->force_writemask_all; const struct intel_device_info *devinfo = shader->devinfo; @@ -1106,7 +1106,7 @@ namespace { scoreboard *sbs = new scoreboard[shader->cfg->num_blocks]; unsigned ip = 0; - foreach_block_and_inst(block, fs_inst, inst, shader->cfg) + foreach_block_and_inst(block, brw_inst, inst, shader->cfg) update_inst_scoreboard(shader, jps, inst, ip++, sbs[block->num]); return sbs; @@ -1145,7 +1145,7 @@ namespace { delta[p] = jps[child_link->block->start_ip].jp[p] - jps[block->end_ip].jp[p] - ordered_unit(shader->devinfo, - static_cast(block->end()), p); + static_cast(block->end()), p); in_sb = merge(eq, in_sb, transport(sb, delta)); } @@ -1177,7 +1177,7 @@ namespace { dependency_list *deps = new dependency_list[num_instructions(shader)]; unsigned ip = 0; - foreach_block_and_inst(block, fs_inst, inst, shader->cfg) { + foreach_block_and_inst(block, brw_inst, inst, shader->cfg) { const bool exec_all = inst->force_writemask_all; const tgl_pipe p = inferred_exec_pipe(devinfo, inst); scoreboard &sb = sbs[block->num]; @@ -1295,7 +1295,7 @@ namespace { const struct intel_device_info *devinfo = shader->devinfo; unsigned ip = 0; - foreach_block_and_inst_safe(block, fs_inst, inst, shader->cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, shader->cfg) { const bool exec_all = inst->force_writemask_all; const bool ordered_mode = baked_ordered_dependency_mode(devinfo, inst, deps[ip], jps[ip]); @@ -1324,7 +1324,7 @@ namespace { */ const brw_builder ibld = brw_builder(shader, block, inst) .exec_all().group(1, 0); - fs_inst *sync = ibld.SYNC(TGL_SYNC_NOP); + brw_inst *sync = ibld.SYNC(TGL_SYNC_NOP); sync->sched.sbid = dep.id; sync->sched.mode = dep.unordered; assert(!(sync->sched.mode & TGL_SBID_SET)); @@ -1347,7 +1347,7 @@ namespace { */ const brw_builder ibld = brw_builder(shader, block, inst) .exec_all().group(1, 0); - fs_inst *sync = ibld.SYNC(TGL_SYNC_NOP); + brw_inst *sync = ibld.SYNC(TGL_SYNC_NOP); sync->sched = ordered_dependency_swsb(deps[ip], jps[ip], true); break; } diff --git a/src/intel/compiler/brw_lower_simd_width.cpp b/src/intel/compiler/brw_lower_simd_width.cpp index b7fe4e01768..11cd343711c 100644 --- a/src/intel/compiler/brw_lower_simd_width.cpp +++ b/src/intel/compiler/brw_lower_simd_width.cpp @@ -9,7 +9,7 @@ using namespace brw; static bool -is_mixed_float_with_fp32_dst(const fs_inst *inst) +is_mixed_float_with_fp32_dst(const brw_inst *inst) { if (inst->dst.type != BRW_TYPE_F) return false; @@ -23,7 +23,7 @@ is_mixed_float_with_fp32_dst(const fs_inst *inst) } static bool -is_mixed_float_with_packed_fp16_dst(const fs_inst *inst) +is_mixed_float_with_packed_fp16_dst(const brw_inst *inst) { if (inst->dst.type != BRW_TYPE_HF || inst->dst.stride != 1) return false; @@ -52,7 +52,7 @@ is_mixed_float_with_packed_fp16_dst(const fs_inst *inst) */ static unsigned get_fpu_lowered_simd_width(const fs_visitor *shader, - const fs_inst *inst) + const brw_inst *inst) { const struct brw_compiler *compiler = shader->compiler; const struct intel_device_info *devinfo = compiler->devinfo; @@ -159,7 +159,7 @@ get_fpu_lowered_simd_width(const fs_visitor *shader, */ static unsigned get_sampler_lowered_simd_width(const struct intel_device_info *devinfo, - const fs_inst *inst) + const brw_inst *inst) { /* If we have a min_lod parameter on anything other than a simple sample * message, it will push it over 5 arguments and we have to fall back to @@ -222,7 +222,7 @@ get_sampler_lowered_simd_width(const struct intel_device_info *devinfo, } static bool -is_half_float_src_dst(const fs_inst *inst) +is_half_float_src_dst(const brw_inst *inst) { if (inst->dst.type == BRW_TYPE_HF) return true; @@ -242,7 +242,7 @@ is_half_float_src_dst(const fs_inst *inst) * original execution size. */ unsigned -brw_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) +brw_get_lowered_simd_width(const fs_visitor *shader, const brw_inst *inst) { const struct brw_compiler *compiler = shader->compiler; const struct intel_device_info *devinfo = compiler->devinfo; @@ -470,7 +470,7 @@ brw_get_lowered_simd_width(const fs_visitor *shader, const fs_inst *inst) * of the lowered instruction. */ static inline bool -needs_src_copy(const brw_builder &lbld, const fs_inst *inst, unsigned i) +needs_src_copy(const brw_builder &lbld, const brw_inst *inst, unsigned i) { /* The indirectly indexed register stays the same even if we split the * instruction. @@ -492,7 +492,7 @@ needs_src_copy(const brw_builder &lbld, const fs_inst *inst, unsigned i) * it as result in packed form. */ static brw_reg -emit_unzip(const brw_builder &lbld, fs_inst *inst, unsigned i) +emit_unzip(const brw_builder &lbld, brw_inst *inst, unsigned i) { assert(lbld.group() >= inst->group); @@ -537,7 +537,7 @@ emit_unzip(const brw_builder &lbld, fs_inst *inst, unsigned i) * destination region. */ static inline bool -needs_dst_copy(const brw_builder &lbld, const fs_inst *inst) +needs_dst_copy(const brw_builder &lbld, const brw_inst *inst) { if (inst->dst.is_null()) return false; @@ -581,7 +581,7 @@ needs_dst_copy(const brw_builder &lbld, const fs_inst *inst) */ static brw_reg emit_zip(const brw_builder &lbld_before, const brw_builder &lbld_after, - fs_inst *inst) + brw_inst *inst) { assert(lbld_before.dispatch_width() == lbld_after.dispatch_width()); assert(lbld_before.group() == lbld_after.group()); @@ -650,7 +650,7 @@ brw_lower_simd_width(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { const unsigned lower_width = brw_get_lowered_simd_width(&s, inst); /* No splitting required */ @@ -729,7 +729,7 @@ brw_lower_simd_width(fs_visitor &s) * If the EOT flag was set throw it away except for the last * instruction to avoid killing the thread prematurely. */ - fs_inst split_inst = *inst; + brw_inst split_inst = *inst; split_inst.exec_size = lower_width; split_inst.eot = inst->eot && i == int(n - 1); diff --git a/src/intel/compiler/brw_lower_subgroup_ops.cpp b/src/intel/compiler/brw_lower_subgroup_ops.cpp index e915347b74f..d9895f53ac8 100644 --- a/src/intel/compiler/brw_lower_subgroup_ops.cpp +++ b/src/intel/compiler/brw_lower_subgroup_ops.cpp @@ -251,7 +251,7 @@ brw_emit_scan(const brw_builder &bld, enum opcode opcode, const brw_reg &tmp, } static bool -brw_lower_reduce(fs_visitor &s, bblock_t *block, fs_inst *inst) +brw_lower_reduce(fs_visitor &s, bblock_t *block, brw_inst *inst) { const brw_builder bld(&s, block, inst); @@ -303,7 +303,7 @@ brw_lower_reduce(fs_visitor &s, bblock_t *block, fs_inst *inst) } static bool -brw_lower_scan(fs_visitor &s, bblock_t *block, fs_inst *inst) +brw_lower_scan(fs_visitor &s, bblock_t *block, brw_inst *inst) { const brw_builder bld(&s, block, inst); @@ -438,7 +438,7 @@ brw_lower_quad_vote_gfx9(const brw_builder &bld, enum opcode opcode, brw_reg dst const enum brw_predicate pred = any ? BRW_PREDICATE_ALIGN1_ANY4H : BRW_PREDICATE_ALIGN1_ALL4H; - fs_inst *mov = bld.MOV(retype(dst, BRW_TYPE_D), brw_imm_d(-1)); + brw_inst *mov = bld.MOV(retype(dst, BRW_TYPE_D), brw_imm_d(-1)); set_predicate(pred, mov); } @@ -488,7 +488,7 @@ brw_lower_quad_vote_gfx20(const brw_builder &bld, enum opcode opcode, brw_reg ds } static bool -brw_lower_vote(fs_visitor &s, bblock_t *block, fs_inst *inst) +brw_lower_vote(fs_visitor &s, bblock_t *block, brw_inst *inst) { const brw_builder bld(&s, block, inst); @@ -518,7 +518,7 @@ brw_lower_vote(fs_visitor &s, bblock_t *block, fs_inst *inst) } static bool -brw_lower_ballot(fs_visitor &s, bblock_t *block, fs_inst *inst) +brw_lower_ballot(fs_visitor &s, bblock_t *block, brw_inst *inst) { const brw_builder bld(&s, block, inst); @@ -548,7 +548,7 @@ brw_lower_ballot(fs_visitor &s, bblock_t *block, fs_inst *inst) } static bool -brw_lower_quad_swap(fs_visitor &s, bblock_t *block, fs_inst *inst) +brw_lower_quad_swap(fs_visitor &s, bblock_t *block, brw_inst *inst) { const brw_builder bld(&s, block, inst); @@ -604,7 +604,7 @@ brw_lower_quad_swap(fs_visitor &s, bblock_t *block, fs_inst *inst) } static bool -brw_lower_read_from_live_channel(fs_visitor &s, bblock_t *block, fs_inst *inst) +brw_lower_read_from_live_channel(fs_visitor &s, bblock_t *block, brw_inst *inst) { const brw_builder bld(&s, block, inst); @@ -620,7 +620,7 @@ brw_lower_read_from_live_channel(fs_visitor &s, bblock_t *block, fs_inst *inst) } static bool -brw_lower_read_from_channel(fs_visitor &s, bblock_t *block, fs_inst *inst) +brw_lower_read_from_channel(fs_visitor &s, bblock_t *block, brw_inst *inst) { const brw_builder bld(&s, block, inst); @@ -657,7 +657,7 @@ brw_lower_subgroup_ops(fs_visitor &s) { bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { switch (inst->opcode) { case SHADER_OPCODE_REDUCE: progress |= brw_lower_reduce(s, block, inst); diff --git a/src/intel/compiler/brw_opt.cpp b/src/intel/compiler/brw_opt.cpp index f3953335e6e..b49381c4637 100644 --- a/src/intel/compiler/brw_opt.cpp +++ b/src/intel/compiler/brw_opt.cpp @@ -207,7 +207,7 @@ brw_optimize(fs_visitor &s) } static unsigned -load_payload_sources_read_for_size(fs_inst *lp, unsigned size_read) +load_payload_sources_read_for_size(brw_inst *lp, unsigned size_read) { assert(lp->opcode == SHADER_OPCODE_LOAD_PAYLOAD); assert(size_read >= lp->header_size * REG_SIZE); @@ -236,7 +236,7 @@ brw_opt_zero_samples(fs_visitor &s) { bool progress = false; - foreach_block_and_inst(block, fs_inst, send, s.cfg) { + foreach_block_and_inst(block, brw_inst, send, s.cfg) { if (send->opcode != SHADER_OPCODE_SEND || send->sfid != BRW_SFID_SAMPLER) continue; @@ -253,7 +253,7 @@ brw_opt_zero_samples(fs_visitor &s) if (send->ex_mlen > 0) continue; - fs_inst *lp = (fs_inst *) send->prev; + brw_inst *lp = (brw_inst *) send->prev; if (lp->is_head_sentinel() || lp->opcode != SHADER_OPCODE_LOAD_PAYLOAD) continue; @@ -313,14 +313,14 @@ brw_opt_split_sends(fs_visitor &s) { bool progress = false; - foreach_block_and_inst(block, fs_inst, send, s.cfg) { + foreach_block_and_inst(block, brw_inst, send, s.cfg) { if (send->opcode != SHADER_OPCODE_SEND || send->mlen <= reg_unit(s.devinfo) || send->ex_mlen > 0 || send->src[2].file != VGRF) continue; /* Currently don't split sends that reuse a previously used payload. */ - fs_inst *lp = (fs_inst *) send->prev; + brw_inst *lp = (brw_inst *) send->prev; if (lp->is_head_sentinel() || lp->opcode != SHADER_OPCODE_LOAD_PAYLOAD) continue; @@ -354,8 +354,8 @@ brw_opt_split_sends(fs_visitor &s) continue; const brw_builder ibld(&s, block, lp); - fs_inst *lp1 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[0], mid, lp->header_size); - fs_inst *lp2 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[mid], end - mid, 0); + brw_inst *lp1 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[0], mid, lp->header_size); + brw_inst *lp2 = ibld.LOAD_PAYLOAD(lp->dst, &lp->src[mid], end - mid, 0); assert(lp1->size_written % REG_SIZE == 0); assert(lp2->size_written % REG_SIZE == 0); @@ -394,9 +394,9 @@ brw_opt_remove_redundant_halts(fs_visitor &s) bool progress = false; unsigned halt_count = 0; - fs_inst *halt_target = NULL; + brw_inst *halt_target = NULL; bblock_t *halt_target_block = NULL; - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { if (inst->opcode == BRW_OPCODE_HALT) halt_count++; @@ -413,9 +413,9 @@ brw_opt_remove_redundant_halts(fs_visitor &s) } /* Delete any HALTs immediately before the halt target. */ - for (fs_inst *prev = (fs_inst *) halt_target->prev; + for (brw_inst *prev = (brw_inst *) halt_target->prev; !prev->is_head_sentinel() && prev->opcode == BRW_OPCODE_HALT; - prev = (fs_inst *) halt_target->prev) { + prev = (brw_inst *) halt_target->prev) { prev->remove(halt_target_block); halt_count--; progress = true; @@ -452,7 +452,7 @@ brw_opt_eliminate_find_live_channel(fs_visitor &s) return false; } - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { switch (inst->opcode) { case BRW_OPCODE_IF: case BRW_OPCODE_DO: @@ -491,7 +491,7 @@ brw_opt_eliminate_find_live_channel(fs_visitor &s) * and opt_algebraic by trivially cleaning up both together. */ assert(!inst->next->is_tail_sentinel()); - fs_inst *bcast = (fs_inst *) inst->next; + brw_inst *bcast = (brw_inst *) inst->next; /* Ignore stride when comparing */ if (bcast->opcode == SHADER_OPCODE_BROADCAST && @@ -552,7 +552,7 @@ brw_opt_remove_extra_rounding_modes(fs_visitor &s) foreach_block (block, s.cfg) { brw_rnd_mode prev_mode = base_mode; - foreach_inst_in_block_safe (fs_inst, inst, block) { + foreach_inst_in_block_safe (brw_inst, inst, block) { if (inst->opcode == SHADER_OPCODE_RND_MODE) { assert(inst->src[0].file == IMM); const brw_rnd_mode mode = (brw_rnd_mode) inst->src[0].d; @@ -585,7 +585,7 @@ brw_opt_send_to_send_gather(fs_visitor &s) unsigned count = 0; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode != SHADER_OPCODE_SEND) continue; @@ -664,7 +664,7 @@ brw_opt_send_gather_to_send(fs_visitor &s) const unsigned unit = reg_unit(devinfo); assert(unit == 2); - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode != SHADER_OPCODE_SEND_GATHER) continue; diff --git a/src/intel/compiler/brw_opt_address_reg_load.cpp b/src/intel/compiler/brw_opt_address_reg_load.cpp index 4d2cc58cbd1..79318af275c 100644 --- a/src/intel/compiler/brw_opt_address_reg_load.cpp +++ b/src/intel/compiler/brw_opt_address_reg_load.cpp @@ -27,11 +27,11 @@ opt_address_reg_load_local(fs_visitor &s, bblock_t *block, const brw::def_analys { bool progress = false; - foreach_inst_in_block_safe(fs_inst, inst, block) { + foreach_inst_in_block_safe(brw_inst, inst, block) { if (!inst->dst.is_address() || inst->opcode != BRW_OPCODE_MOV) continue; - fs_inst *src_inst = defs.get(inst->src[0]); + brw_inst *src_inst = defs.get(inst->src[0]); if (src_inst == NULL) continue; @@ -61,7 +61,7 @@ brw_opt_address_reg_load(fs_visitor &s) const brw::def_analysis &defs = s.def_analysis.require(); foreach_block(block, s.cfg) { - foreach_inst_in_block_safe(fs_inst, inst, block) { + foreach_inst_in_block_safe(brw_inst, inst, block) { progress = opt_address_reg_load_local(s, block, defs) || progress; } } diff --git a/src/intel/compiler/brw_opt_algebraic.cpp b/src/intel/compiler/brw_opt_algebraic.cpp index b9038455944..56b7a391922 100644 --- a/src/intel/compiler/brw_opt_algebraic.cpp +++ b/src/intel/compiler/brw_opt_algebraic.cpp @@ -89,7 +89,7 @@ brw_imm_for_type(uint64_t value, enum brw_reg_type type) * Converts a MAD to an ADD by folding the multiplicand sources. */ static void -fold_multiplicands_of_MAD(fs_inst *inst) +fold_multiplicands_of_MAD(brw_inst *inst) { assert(inst->opcode == BRW_OPCODE_MAD); assert (inst->src[1].file == IMM && @@ -135,7 +135,7 @@ fold_multiplicands_of_MAD(fs_inst *inst) } bool -brw_opt_constant_fold_instruction(const intel_device_info *devinfo, fs_inst *inst) +brw_opt_constant_fold_instruction(const intel_device_info *devinfo, brw_inst *inst) { bool progress = false; @@ -325,7 +325,7 @@ brw_opt_algebraic(fs_visitor &s) const intel_device_info *devinfo = s.devinfo; bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (brw_opt_constant_fold_instruction(devinfo, inst)) { progress = true; continue; diff --git a/src/intel/compiler/brw_opt_bank_conflicts.cpp b/src/intel/compiler/brw_opt_bank_conflicts.cpp index 28b32870dbe..78ef0d029ca 100644 --- a/src/intel/compiler/brw_opt_bank_conflicts.cpp +++ b/src/intel/compiler/brw_opt_bank_conflicts.cpp @@ -511,7 +511,7 @@ namespace { { partitioning p(BRW_MAX_GRF); - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { + foreach_block_and_inst(block, brw_inst, inst, v->cfg) { if (is_grf(inst->dst)) p.require_contiguous(reg_of(inst->dst), regs_written(inst)); @@ -552,7 +552,7 @@ namespace { */ constrained[p.atom_of_reg(127)] = true; - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { + foreach_block_and_inst(block, brw_inst, inst, v->cfg) { /* Assume that anything referenced via fixed GRFs is baked into the * hardware's fixed-function logic and may be unsafe to move around. * Also take into account the source GRF restrictions of EOT @@ -578,7 +578,7 @@ namespace { */ bool is_conflict_optimized_out(const intel_device_info *devinfo, - const fs_inst *inst) + const brw_inst *inst) { return (is_grf(inst->src[0]) && (reg_of(inst->src[0]) == reg_of(inst->src[1]) || @@ -618,7 +618,7 @@ namespace { */ unsigned block_scale = 1; - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { + foreach_block_and_inst(block, brw_inst, inst, v->cfg) { if (inst->opcode == BRW_OPCODE_DO) { block_scale *= 10; @@ -903,7 +903,7 @@ brw_opt_bank_conflicts(fs_visitor &s) optimize_reg_permutation(p, constrained, conflicts, identity_reg_permutation(p)); - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { inst->dst = transform(p, map, inst->dst); for (int i = 0; i < inst->sources; i++) @@ -922,7 +922,7 @@ brw_opt_bank_conflicts(fs_visitor &s) * we don't know which bank each VGRF is going to end up aligned to. */ bool -has_bank_conflict(const struct brw_isa_info *isa, const fs_inst *inst) +has_bank_conflict(const struct brw_isa_info *isa, const brw_inst *inst) { return is_3src(isa, inst->opcode) && is_grf(inst->src[1]) && is_grf(inst->src[2]) && diff --git a/src/intel/compiler/brw_opt_cmod_propagation.cpp b/src/intel/compiler/brw_opt_cmod_propagation.cpp index 22991cb2215..87878aa865d 100644 --- a/src/intel/compiler/brw_opt_cmod_propagation.cpp +++ b/src/intel/compiler/brw_opt_cmod_propagation.cpp @@ -52,12 +52,12 @@ using namespace brw; static bool cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block, - fs_inst *inst) + brw_inst *inst) { bool read_flag = false; const unsigned flags_written = inst->flags_written(devinfo); - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(brw_inst, scan_inst, inst) { if (scan_inst->opcode == BRW_OPCODE_ADD && !scan_inst->predicate && scan_inst->dst.is_contiguous() && @@ -169,7 +169,7 @@ cmod_propagate_cmp_to_add(const intel_device_info *devinfo, bblock_t *block, */ static bool cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block, - fs_inst *inst) + brw_inst *inst) { const enum brw_conditional_mod cond = brw_negate_cmod(inst->conditional_mod); bool read_flag = false; @@ -178,7 +178,7 @@ cmod_propagate_not(const intel_device_info *devinfo, bblock_t *block, if (cond != BRW_CONDITIONAL_Z && cond != BRW_CONDITIONAL_NZ) return false; - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(brw_inst, scan_inst, inst) { if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(devinfo, 0))) { if (scan_inst->opcode != BRW_OPCODE_OR && @@ -229,7 +229,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) bool progress = false; UNUSED int ip = block->end_ip + 1; - foreach_inst_in_block_reverse_safe(fs_inst, inst, block) { + foreach_inst_in_block_reverse_safe(brw_inst, inst, block) { ip--; if ((inst->opcode != BRW_OPCODE_AND && @@ -286,7 +286,7 @@ opt_cmod_propagation_local(const intel_device_info *devinfo, bblock_t *block) bool read_flag = false; const unsigned flags_written = inst->flags_written(devinfo); - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(brw_inst, scan_inst, inst) { if (regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(devinfo, 0))) { /* If the scan instruction writes a different flag register than diff --git a/src/intel/compiler/brw_opt_combine_constants.cpp b/src/intel/compiler/brw_opt_combine_constants.cpp index 33ab66e08b8..3b93f999ded 100644 --- a/src/intel/compiler/brw_opt_combine_constants.cpp +++ b/src/intel/compiler/brw_opt_combine_constants.cpp @@ -759,12 +759,12 @@ brw_combine_constants(struct value *candidates, unsigned num_candidates) } /** - * Box for storing fs_inst and some other necessary data + * Box for storing brw_inst and some other necessary data * * \sa box_instruction */ struct fs_inst_box { - fs_inst *inst; + brw_inst *inst; unsigned ip; bblock_t *block; }; @@ -773,18 +773,18 @@ struct fs_inst_box { struct reg_link { DECLARE_RALLOC_CXX_OPERATORS(reg_link) - reg_link(fs_inst *inst, unsigned src, bool negate, enum interpreted_type type) + reg_link(brw_inst *inst, unsigned src, bool negate, enum interpreted_type type) : inst(inst), src(src), negate(negate), type(type) {} struct exec_node link; - fs_inst *inst; + brw_inst *inst; uint8_t src; bool negate; enum interpreted_type type; }; static struct exec_node * -link(void *mem_ctx, fs_inst *inst, unsigned src, bool negate, +link(void *mem_ctx, brw_inst *inst, unsigned src, bool negate, enum interpreted_type type) { reg_link *l = new(mem_ctx) reg_link(inst, src, negate, type); @@ -802,7 +802,7 @@ struct imm { * The instruction generating the immediate value, if all uses are contained * within a single basic block. Otherwise, NULL. */ - fs_inst *inst; + brw_inst *inst; /** * A list of fs_regs that refer to this immediate. If we promote it, we'll @@ -868,7 +868,7 @@ new_value(struct table *table, void *mem_ctx) * \returns the index into the dynamic array of boxes for the instruction. */ static unsigned -box_instruction(struct table *table, void *mem_ctx, fs_inst *inst, +box_instruction(struct table *table, void *mem_ctx, brw_inst *inst, unsigned ip, bblock_t *block) { /* It is common for box_instruction to be called consecutively for each @@ -989,7 +989,7 @@ representable_as_uw(unsigned ud, uint16_t *uw) } static bool -supports_src_as_imm(const struct intel_device_info *devinfo, const fs_inst *inst, +supports_src_as_imm(const struct intel_device_info *devinfo, const brw_inst *inst, unsigned src_idx) { switch (inst->opcode) { @@ -1051,7 +1051,7 @@ supports_src_as_imm(const struct intel_device_info *devinfo, const fs_inst *inst } static bool -can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst, +can_promote_src_as_imm(const struct intel_device_info *devinfo, brw_inst *inst, unsigned src_idx) { bool can_promote = false; @@ -1107,7 +1107,7 @@ can_promote_src_as_imm(const struct intel_device_info *devinfo, fs_inst *inst, } static void -add_candidate_immediate(struct table *table, fs_inst *inst, unsigned ip, +add_candidate_immediate(struct table *table, brw_inst *inst, unsigned ip, unsigned i, bool allow_one_constant, bblock_t *block, @@ -1316,7 +1316,7 @@ brw_opt_combine_constants(fs_visitor &s) /* Make a pass through all instructions and mark each constant is used in * instruction sources that cannot legally be immediate values. */ - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { ip++; switch (inst->opcode) { @@ -1718,7 +1718,7 @@ brw_opt_combine_constants(fs_visitor &s) * so the other source (and destination) must be changed to match. */ for (unsigned i = 0; i < table.num_boxes; i++) { - fs_inst *inst = table.boxes[i].inst; + brw_inst *inst = table.boxes[i].inst; if (inst->opcode != BRW_OPCODE_SEL) continue; diff --git a/src/intel/compiler/brw_opt_copy_propagation.cpp b/src/intel/compiler/brw_opt_copy_propagation.cpp index 94744b798a9..e4dfcaf2827 100644 --- a/src/intel/compiler/brw_opt_copy_propagation.cpp +++ b/src/intel/compiler/brw_opt_copy_propagation.cpp @@ -376,7 +376,7 @@ fs_copy_prop_dataflow::setup_initial_values() acp_table.add(acp[i]); foreach_block (block, cfg) { - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(brw_inst, inst, block) { if (inst->dst.file != VGRF && inst->dst.file != FIXED_GRF) continue; @@ -579,7 +579,7 @@ is_logic_op(enum opcode opcode) } static bool -can_take_stride(fs_inst *inst, brw_reg_type dst_type, +can_take_stride(brw_inst *inst, brw_reg_type dst_type, unsigned arg, unsigned stride, const struct brw_compiler *compiler) { @@ -643,7 +643,7 @@ can_take_stride(fs_inst *inst, brw_reg_type dst_type, } static bool -instruction_requires_packed_data(fs_inst *inst) +instruction_requires_packed_data(brw_inst *inst) { switch (inst->opcode) { case FS_OPCODE_DDX_FINE: @@ -659,7 +659,7 @@ instruction_requires_packed_data(fs_inst *inst) } static bool -try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, +try_copy_propagate(const brw_compiler *compiler, brw_inst *inst, acp_entry *entry, int arg, const brw::simple_allocator &alloc, uint8_t max_polygons) @@ -940,7 +940,7 @@ try_copy_propagate(const brw_compiler *compiler, fs_inst *inst, static bool try_constant_propagate_value(brw_reg val, brw_reg_type dst_type, - fs_inst *inst, int arg) + brw_inst *inst, int arg) { bool progress = false; @@ -1212,7 +1212,7 @@ try_constant_propagate_value(brw_reg val, brw_reg_type dst_type, static bool try_constant_propagate(const struct intel_device_info *devinfo, - fs_inst *inst, acp_entry *entry, int arg) + brw_inst *inst, acp_entry *entry, int arg) { if (inst->src[arg].file != VGRF) return false; @@ -1240,7 +1240,7 @@ try_constant_propagate(const struct intel_device_info *devinfo, } static bool -can_propagate_from(const struct intel_device_info *devinfo, fs_inst *inst) +can_propagate_from(const struct intel_device_info *devinfo, brw_inst *inst) { return (inst->opcode == BRW_OPCODE_MOV && inst->dst.file == VGRF && @@ -1264,7 +1264,7 @@ can_propagate_from(const struct intel_device_info *devinfo, fs_inst *inst) } static void -swap_srcs(fs_inst *inst, unsigned a, unsigned b) +swap_srcs(brw_inst *inst, unsigned a, unsigned b) { const auto tmp = inst->src[a]; inst->src[a] = inst->src[b]; @@ -1272,7 +1272,7 @@ swap_srcs(fs_inst *inst, unsigned a, unsigned b) } static void -commute_immediates(fs_inst *inst) +commute_immediates(brw_inst *inst) { /* ADD3 can have the immediate as src0 or src2. Using one or the other * consistently makes assembly dumps more readable, so we arbitrarily @@ -1317,7 +1317,7 @@ opt_copy_propagation_local(const brw_compiler *compiler, linear_ctx *lin_ctx, const struct intel_device_info *devinfo = compiler->devinfo; bool progress = false; - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(brw_inst, inst, block) { /* Try propagating into this instruction. */ bool constant_progress = false; for (int i = inst->sources - 1; i >= 0; i--) { @@ -1488,8 +1488,8 @@ brw_opt_copy_propagation(fs_visitor &s) static bool try_copy_propagate_def(const brw_compiler *compiler, const brw::simple_allocator &alloc, - fs_inst *def, const brw_reg &val, - fs_inst *inst, int arg, + brw_inst *def, const brw_reg &val, + brw_inst *inst, int arg, uint8_t max_polygons) { const struct intel_device_info *devinfo = compiler->devinfo; @@ -1723,7 +1723,7 @@ try_copy_propagate_def(const brw_compiler *compiler, static bool try_constant_propagate_def(const struct intel_device_info *devinfo, - fs_inst *def, brw_reg val, fs_inst *inst, int arg) + brw_inst *def, brw_reg val, brw_inst *inst, int arg) { /* Bail if inst is reading more than a single vector component of entry */ if (inst->size_read(devinfo, arg) > def->dst.component_size(inst->exec_size)) @@ -1753,7 +1753,7 @@ extract_imm(brw_reg val, brw_reg_type type, unsigned offset) } static brw_reg -find_value_for_offset(fs_inst *def, const brw_reg &src, unsigned src_size) +find_value_for_offset(brw_inst *def, const brw_reg &src, unsigned src_size) { brw_reg val; @@ -1816,12 +1816,12 @@ brw_opt_copy_propagation_defs(fs_visitor &s) unsigned *uses_deleted = new unsigned[defs.count()](); bool progress = false; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { /* Try propagating into this instruction. */ bool constant_progress = false; for (int i = inst->sources - 1; i >= 0; i--) { - fs_inst *def = defs.get(inst->src[i]); + brw_inst *def = defs.get(inst->src[i]); if (!def || def->saturate) continue; diff --git a/src/intel/compiler/brw_opt_cse.cpp b/src/intel/compiler/brw_opt_cse.cpp index 8af765d6f93..6e62f64cbc1 100644 --- a/src/intel/compiler/brw_opt_cse.cpp +++ b/src/intel/compiler/brw_opt_cse.cpp @@ -36,7 +36,7 @@ using namespace brw; struct remap_entry { - fs_inst *inst; + brw_inst *inst; bblock_t *block; enum brw_reg_type type; unsigned nr; @@ -45,7 +45,7 @@ struct remap_entry { }; static bool -is_expression(const fs_visitor *v, const fs_inst *const inst) +is_expression(const fs_visitor *v, const brw_inst *const inst) { switch (inst->opcode) { case BRW_OPCODE_MOV: @@ -144,7 +144,7 @@ is_expression(const fs_visitor *v, const fs_inst *const inst) * True if the instruction should only be CSE'd within their local block. */ bool -local_only(const fs_inst *inst) +local_only(const brw_inst *inst) { switch (inst->opcode) { case SHADER_OPCODE_FIND_LIVE_CHANNEL: @@ -172,7 +172,7 @@ local_only(const fs_inst *inst) } static bool -operands_match(const fs_inst *a, const fs_inst *b, bool *negate) +operands_match(const brw_inst *a, const brw_inst *b, bool *negate) { brw_reg *xs = a->src; brw_reg *ys = b->src; @@ -235,7 +235,7 @@ operands_match(const fs_inst *a, const fs_inst *b, bool *negate) } static bool -instructions_match(fs_inst *a, fs_inst *b, bool *negate) +instructions_match(brw_inst *a, brw_inst *b, bool *negate) { return a->opcode == b->opcode && a->exec_size == b->exec_size && @@ -281,7 +281,7 @@ hash_reg(uint32_t hash, const brw_reg &r) static uint32_t hash_inst(const void *v) { - const fs_inst *inst = static_cast(v); + const brw_inst *inst = static_cast(v); uint32_t hash = 0; /* Skip dst - that would make nothing ever match */ @@ -359,12 +359,12 @@ static bool cmp_func(const void *data1, const void *data2) { bool negate; - return instructions_match((fs_inst *) data1, (fs_inst *) data2, &negate); + return instructions_match((brw_inst *) data1, (brw_inst *) data2, &negate); } static bool remap_sources(fs_visitor &s, const brw::def_analysis &defs, - fs_inst *inst, struct remap_entry *remap_table) + brw_inst *inst, struct remap_entry *remap_table) { bool progress = false; @@ -409,10 +409,10 @@ brw_opt_cse_defs(fs_visitor &s) struct set *set = _mesa_set_create(NULL, NULL, cmp_func); foreach_block(block, s.cfg) { - fs_inst *last_flag_write = NULL; - fs_inst *last = NULL; + brw_inst *last_flag_write = NULL; + brw_inst *last = NULL; - foreach_inst_in_block_safe(fs_inst, inst, block) { + foreach_inst_in_block_safe(brw_inst, inst, block) { if (need_remaps) progress |= remap_sources(s, defs, inst, remap_table); @@ -448,7 +448,7 @@ brw_opt_cse_defs(fs_visitor &s) struct set_entry *e = _mesa_set_search_or_add_pre_hashed(set, hash, inst, NULL); if (!e) goto out; /* out of memory error */ - fs_inst *match = (fs_inst *) e->key; + brw_inst *match = (brw_inst *) e->key; /* If there was no match, move on */ if (match == inst) diff --git a/src/intel/compiler/brw_opt_dead_code_eliminate.cpp b/src/intel/compiler/brw_opt_dead_code_eliminate.cpp index e709d7d33c5..d2e28b40695 100644 --- a/src/intel/compiler/brw_opt_dead_code_eliminate.cpp +++ b/src/intel/compiler/brw_opt_dead_code_eliminate.cpp @@ -40,7 +40,7 @@ using namespace brw; * Is it safe to eliminate the instruction? */ static bool -can_eliminate(const intel_device_info *devinfo, const fs_inst *inst, +can_eliminate(const intel_device_info *devinfo, const brw_inst *inst, BITSET_WORD *flag_live) { return !inst->is_control_flow() && @@ -53,7 +53,7 @@ can_eliminate(const intel_device_info *devinfo, const fs_inst *inst, * Is it safe to omit the write, making the destination ARF null? */ static bool -can_omit_write(const fs_inst *inst) +can_omit_write(const brw_inst *inst) { switch (inst->opcode) { case SHADER_OPCODE_MEMORY_ATOMIC_LOGICAL: @@ -72,7 +72,7 @@ can_omit_write(const fs_inst *inst) static bool can_eliminate_conditional_mod(const intel_device_info *devinfo, - const fs_inst *inst, BITSET_WORD *flag_live) + const brw_inst *inst, BITSET_WORD *flag_live) { /* CMP, CMPN, and CSEL must have a conditional modifier because the * modifier determines what the instruction does. SEL with a conditional @@ -114,7 +114,7 @@ brw_opt_dead_code_eliminate(fs_visitor &s) memcpy(flag_live, live_vars.block_data[block->num].flag_liveout, sizeof(BITSET_WORD)); - foreach_inst_in_block_reverse_safe(fs_inst, inst, block) { + foreach_inst_in_block_reverse_safe(brw_inst, inst, block) { if (inst->dst.file == VGRF) { const unsigned var = live_vars.var_from_reg(inst->dst); bool result_live = false; diff --git a/src/intel/compiler/brw_opt_register_coalesce.cpp b/src/intel/compiler/brw_opt_register_coalesce.cpp index 240cdb9e311..decd144a9b6 100644 --- a/src/intel/compiler/brw_opt_register_coalesce.cpp +++ b/src/intel/compiler/brw_opt_register_coalesce.cpp @@ -47,7 +47,7 @@ using namespace brw; static bool -is_nop_mov(const fs_inst *inst) +is_nop_mov(const brw_inst *inst) { if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { brw_reg dst = inst->dst; @@ -68,7 +68,7 @@ is_nop_mov(const fs_inst *inst) } static bool -is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst) +is_coalesce_candidate(const fs_visitor *v, const brw_inst *inst) { if ((inst->opcode != BRW_OPCODE_MOV && inst->opcode != SHADER_OPCODE_LOAD_PAYLOAD) || @@ -99,7 +99,7 @@ is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst) static bool can_coalesce_vars(const intel_device_info *devinfo, const fs_live_variables &live, const cfg_t *cfg, - const bblock_t *block, const fs_inst *inst, + const bblock_t *block, const brw_inst *inst, int dst_var, int src_var) { if (!live.vars_interfere(src_var, dst_var)) @@ -129,7 +129,7 @@ can_coalesce_vars(const intel_device_info *devinfo, bool seen_src_write = false; bool seen_copy = false; - foreach_inst_in_block(fs_inst, scan_inst, scan_block) { + foreach_inst_in_block(brw_inst, scan_inst, scan_block) { scan_ip++; /* Ignore anything before the intersection of the live ranges */ @@ -199,7 +199,7 @@ would_violate_eot_restriction(const brw::simple_allocator &alloc, unsigned dst_reg, unsigned src_reg) { if (alloc.sizes[dst_reg] > alloc.sizes[src_reg]) { - foreach_inst_in_block_reverse(fs_inst, send, cfg->last_block()) { + foreach_inst_in_block_reverse(brw_inst, send, cfg->last_block()) { if (send->opcode != SHADER_OPCODE_SEND || !send->eot) continue; @@ -236,11 +236,11 @@ brw_opt_register_coalesce(fs_visitor &s) int channels_remaining = 0; unsigned src_reg = ~0u, dst_reg = ~0u; int *dst_reg_offset = new int[MAX_VGRF_SIZE(devinfo)]; - fs_inst **mov = new fs_inst *[MAX_VGRF_SIZE(devinfo)]; + brw_inst **mov = new brw_inst *[MAX_VGRF_SIZE(devinfo)]; int *dst_var = new int[MAX_VGRF_SIZE(devinfo)]; int *src_var = new int[MAX_VGRF_SIZE(devinfo)]; - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { if (!is_coalesce_candidate(&s, inst)) continue; @@ -341,7 +341,7 @@ brw_opt_register_coalesce(fs_visitor &s) } } - foreach_block_and_inst(block, fs_inst, scan_inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, scan_inst, s.cfg) { if (scan_inst->dst.file == VGRF && scan_inst->dst.nr == src_reg) { scan_inst->dst.nr = dst_reg; @@ -369,7 +369,7 @@ brw_opt_register_coalesce(fs_visitor &s) } if (progress) { - foreach_block_and_inst_safe (block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe (block, brw_inst, inst, s.cfg) { if (inst->opcode == BRW_OPCODE_NOP) { inst->remove(block, true); } diff --git a/src/intel/compiler/brw_opt_saturate_propagation.cpp b/src/intel/compiler/brw_opt_saturate_propagation.cpp index 60f1cb37dad..a81d1fea05c 100644 --- a/src/intel/compiler/brw_opt_saturate_propagation.cpp +++ b/src/intel/compiler/brw_opt_saturate_propagation.cpp @@ -45,7 +45,7 @@ using namespace brw; */ static bool -propagate_sat(fs_inst *inst, fs_inst *scan_inst) +propagate_sat(brw_inst *inst, brw_inst *scan_inst) { if (scan_inst->dst.type != inst->dst.type) { scan_inst->dst.type = inst->dst.type; @@ -93,7 +93,7 @@ opt_saturate_propagation_local(fs_visitor &s, bblock_t *block) bool progress = false; int ip = block->end_ip + 1; - foreach_inst_in_block_reverse(fs_inst, inst, block) { + foreach_inst_in_block_reverse(brw_inst, inst, block) { ip--; if (inst->opcode != BRW_OPCODE_MOV || @@ -105,7 +105,7 @@ opt_saturate_propagation_local(fs_visitor &s, bblock_t *block) continue; const brw::def_analysis &defs = s.def_analysis.require(); - fs_inst *def = defs.get(inst->src[0]); + brw_inst *def = defs.get(inst->src[0]); if (def != NULL) { if (def->exec_size != inst->exec_size) @@ -140,7 +140,7 @@ opt_saturate_propagation_local(fs_visitor &s, bblock_t *block) int src_end_ip = live.end[src_var]; bool interfered = false; - foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { + foreach_inst_in_block_reverse_starting_from(brw_inst, scan_inst, inst) { if (scan_inst->exec_size == inst->exec_size && regions_overlap(scan_inst->dst, scan_inst->size_written, inst->src[0], inst->size_read(s.devinfo, 0))) { diff --git a/src/intel/compiler/brw_opt_txf_combiner.cpp b/src/intel/compiler/brw_opt_txf_combiner.cpp index da1a56146fd..ea6ba5b0e75 100644 --- a/src/intel/compiler/brw_opt_txf_combiner.cpp +++ b/src/intel/compiler/brw_opt_txf_combiner.cpp @@ -10,7 +10,7 @@ using namespace brw; static unsigned -dest_comps_for_txf(const fs_visitor &s, const fs_inst *txf) +dest_comps_for_txf(const fs_visitor &s, const brw_inst *txf) { if (!txf) return 0; @@ -43,7 +43,7 @@ is_uniform_def(const def_analysis &defs, const brw_reg &r) */ static bool sources_match(ASSERTED const def_analysis &defs, - const fs_inst *a, const fs_inst *b, enum tex_logical_srcs src) + const brw_inst *a, const brw_inst *b, enum tex_logical_srcs src) { assert(is_def(defs, a->src[src])); assert(is_def(defs, b->src[src])); @@ -92,10 +92,10 @@ brw_opt_combine_convergent_txf(fs_visitor &s) foreach_block(block, s.cfg) { /* Gather a list of convergent TXFs to the same surface in this block */ - fs_inst *txfs[32] = {}; + brw_inst *txfs[32] = {}; unsigned count = 0; - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(brw_inst, inst, block) { if (inst->opcode != SHADER_OPCODE_TXF_LOGICAL) continue; @@ -196,7 +196,7 @@ brw_opt_combine_convergent_txf(fs_visitor &s) /* Emit the new divergent TXF */ brw_reg div = ubld.vgrf(BRW_TYPE_UD, new_dest_comps); - fs_inst *div_txf = + brw_inst *div_txf = ubld.emit(SHADER_OPCODE_TXF_LOGICAL, div, srcs, TEX_LOGICAL_NUM_SRCS); @@ -207,7 +207,7 @@ brw_opt_combine_convergent_txf(fs_visitor &s) div_txf->size_written = new_dest_comps * per_component_regs * grf_size; for (unsigned i = 0; i < width; i++) { - fs_inst *txf = txfs[curr+i]; + brw_inst *txf = txfs[curr+i]; if (!txf) break; diff --git a/src/intel/compiler/brw_opt_virtual_grfs.cpp b/src/intel/compiler/brw_opt_virtual_grfs.cpp index 6e203a01ac6..2bb1769bd38 100644 --- a/src/intel/compiler/brw_opt_virtual_grfs.cpp +++ b/src/intel/compiler/brw_opt_virtual_grfs.cpp @@ -53,7 +53,7 @@ brw_opt_split_virtual_grfs(fs_visitor &s) * register size. */ const unsigned reg_inc = reg_unit(s.devinfo); - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { if (inst->dst.file == VGRF) { unsigned reg = vgrf_to_reg[inst->dst.nr]; for (unsigned j = reg_inc; j < s.alloc.sizes[inst->dst.nr]; j += reg_inc) @@ -69,7 +69,7 @@ brw_opt_split_virtual_grfs(fs_visitor &s) } } - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { /* We fix up undef instructions later */ if (inst->opcode == SHADER_OPCODE_UNDEF) { assert(inst->dst.file == VGRF); @@ -141,7 +141,7 @@ brw_opt_split_virtual_grfs(fs_visitor &s) goto cleanup; } - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (inst->opcode == SHADER_OPCODE_UNDEF) { assert(inst->dst.file == VGRF); if (vgrf_has_split[inst->dst.nr]) { @@ -151,7 +151,7 @@ brw_opt_split_virtual_grfs(fs_visitor &s) unsigned size_written = 0; while (size_written < inst->size_written) { reg = vgrf_to_reg[inst->dst.nr] + reg_offset + size_written / REG_SIZE; - fs_inst *undef = + brw_inst *undef = ibld.UNDEF( byte_offset(brw_vgrf(new_virtual_grf[reg], inst->dst.type), new_reg_offset[reg] * REG_SIZE)); @@ -228,7 +228,7 @@ brw_opt_compact_virtual_grfs(fs_visitor &s) memset(remap_table, -1, s.alloc.count * sizeof(int)); /* Mark which virtual GRFs are used. */ - foreach_block_and_inst(block, const fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, const brw_inst, inst, s.cfg) { if (inst->dst.file == VGRF) remap_table[inst->dst.nr] = 0; @@ -257,7 +257,7 @@ brw_opt_compact_virtual_grfs(fs_visitor &s) s.alloc.count = new_index; /* Patch all the instructions to use the newly renumbered registers */ - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { if (inst->dst.file == VGRF) inst->dst.nr = remap_table[inst->dst.nr]; diff --git a/src/intel/compiler/brw_print.cpp b/src/intel/compiler/brw_print.cpp index 6cdf711dd22..0e5b932d09d 100644 --- a/src/intel/compiler/brw_print.cpp +++ b/src/intel/compiler/brw_print.cpp @@ -31,7 +31,7 @@ brw_print_instructions(const fs_visitor &s, FILE *file) } fprintf(file, "\n"); - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(brw_inst, inst, block) { if (inst->is_control_flow_end()) cf_count -= 1; @@ -60,11 +60,11 @@ brw_print_instructions(const fs_visitor &s, FILE *file) if (rp) fprintf(file, "Maximum %3d registers live at once.\n", max_pressure); } else if (s.cfg && exec_list_is_empty(&s.instructions)) { - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { brw_print_instruction(s, inst, file); } } else { - foreach_in_list(fs_inst, inst, &s.instructions) { + foreach_in_list(brw_inst, inst, &s.instructions) { brw_print_instruction(s, inst, file); } } @@ -308,7 +308,7 @@ brw_instruction_name(const struct brw_isa_info *isa, enum opcode op) * we only printed a label, and the actual source value still needs printing. */ static bool -print_memory_logical_source(FILE *file, const fs_inst *inst, unsigned i) +print_memory_logical_source(FILE *file, const brw_inst *inst, unsigned i) { if (inst->is_control_source(i)) { assert(inst->src[i].file == IMM && inst->src[i].type == BRW_TYPE_UD); @@ -374,7 +374,7 @@ print_memory_logical_source(FILE *file, const fs_inst *inst, unsigned i) } void -brw_print_instruction(const fs_visitor &s, const fs_inst *inst, FILE *file, const brw::def_analysis *defs) +brw_print_instruction(const fs_visitor &s, const brw_inst *inst, FILE *file, const brw::def_analysis *defs) { if (inst->predicate) { fprintf(file, "(%cf%d.%d) ", diff --git a/src/intel/compiler/brw_reg_allocate.cpp b/src/intel/compiler/brw_reg_allocate.cpp index e17b28e10b5..4fa013b470d 100644 --- a/src/intel/compiler/brw_reg_allocate.cpp +++ b/src/intel/compiler/brw_reg_allocate.cpp @@ -61,7 +61,7 @@ brw_assign_regs_trivial(fs_visitor &s) } s.grf_used = hw_reg_mapping[s.alloc.count]; - foreach_block_and_inst(block, fs_inst, inst, s.cfg) { + foreach_block_and_inst(block, brw_inst, inst, s.cfg) { assign_reg(devinfo, hw_reg_mapping, &inst->dst); for (i = 0; i < inst->sources; i++) { assign_reg(devinfo, hw_reg_mapping, &inst->src[i]); @@ -165,7 +165,7 @@ void fs_visitor::calculate_payload_ranges(bool allow_spilling, payload_last_use_ip[i] = -1; int ip = 0; - foreach_block_and_inst(block, fs_inst, inst, cfg) { + foreach_block_and_inst(block, brw_inst, inst, cfg) { switch (inst->opcode) { case BRW_OPCODE_DO: loop_depth++; @@ -286,7 +286,7 @@ public: private: void setup_live_interference(unsigned node, int node_start_ip, int node_end_ip); - void setup_inst_interference(const fs_inst *inst); + void setup_inst_interference(const brw_inst *inst); void build_interference_graph(bool allow_spilling); @@ -426,7 +426,7 @@ brw_reg_alloc::setup_live_interference(unsigned node, * GRF sources and the destination. */ static bool -brw_inst_has_source_and_destination_hazard(const fs_inst *inst) +brw_inst_has_source_and_destination_hazard(const brw_inst *inst) { switch (inst->opcode) { case FS_OPCODE_PACK_HALF_2x16_SPLIT: @@ -519,7 +519,7 @@ brw_inst_has_source_and_destination_hazard(const fs_inst *inst) } void -brw_reg_alloc::setup_inst_interference(const fs_inst *inst) +brw_reg_alloc::setup_inst_interference(const brw_inst *inst) { /* Certain instructions can't safely use the same register for their * sources and destination. Add interference. @@ -674,7 +674,7 @@ brw_reg_alloc::build_interference_graph(bool allow_spilling) /* Add interference based on the instructions in which a register is used. */ - foreach_block_and_inst(block, fs_inst, inst, fs->cfg) + foreach_block_and_inst(block, brw_inst, inst, fs->cfg) setup_inst_interference(inst); } @@ -682,7 +682,7 @@ brw_reg brw_reg_alloc::build_single_offset(const brw_builder &bld, uint32_t spill_offset, int ip) { brw_reg offset = retype(alloc_spill_reg(1, ip), BRW_TYPE_UD); - fs_inst *inst = bld.MOV(offset, brw_imm_ud(spill_offset)); + brw_inst *inst = bld.MOV(offset, brw_imm_ud(spill_offset)); _mesa_set_add(spill_insts, inst); return offset; } @@ -697,7 +697,7 @@ brw_reg_alloc::build_ex_desc(const brw_builder &bld, unsigned reg_size, bool uns */ brw_reg ex_desc = bld.vaddr(BRW_TYPE_UD, BRW_ADDRESS_SUBREG_INDIRECT_SPILL_DESC); - fs_inst *inst = bld.exec_all().group(1, 0).AND( + brw_inst *inst = bld.exec_all().group(1, 0).AND( ex_desc, retype(brw_vec1_grf(0, 5), BRW_TYPE_UD), brw_imm_ud(INTEL_MASK(31, 10))); @@ -734,7 +734,7 @@ brw_reg_alloc::build_lane_offsets(const brw_builder &bld, uint32_t spill_offset, const unsigned reg_count = ubld.dispatch_width() / 8; brw_reg offset = retype(alloc_spill_reg(reg_count, ip), BRW_TYPE_UD); - fs_inst *inst; + brw_inst *inst; /* Build an offset per lane in SIMD8 */ inst = ubld.group(8, 0).MOV(retype(offset, BRW_TYPE_UW), @@ -788,7 +788,7 @@ brw_reg_alloc::build_legacy_scratch_header(const brw_builder &bld, brw_reg header = retype(alloc_spill_reg(1, ip), BRW_TYPE_UD); ra_add_node_interference(g, first_vgrf_node + header.nr, first_payload_node); - fs_inst *inst = + brw_inst *inst = ubld8.emit(SHADER_OPCODE_SCRATCH_HEADER, header, brw_ud8_grf(0, 0)); _mesa_set_add(spill_insts, inst); @@ -813,7 +813,7 @@ brw_reg_alloc::emit_unspill(const brw_builder &bld, for (unsigned i = 0; i < DIV_ROUND_UP(count, reg_size); i++) { ++stats->fill_count; - fs_inst *unspill_inst; + brw_inst *unspill_inst; if (devinfo->verx10 >= 125) { /* LSC is limited to SIMD16 (SIMD32 on Xe2) load/store but we can * load more using transpose messages. @@ -912,7 +912,7 @@ brw_reg_alloc::emit_spill(const brw_builder &bld, for (unsigned i = 0; i < DIV_ROUND_UP(count, reg_size); i++) { ++stats->spill_count; - fs_inst *spill_inst; + brw_inst *spill_inst; if (devinfo->verx10 >= 125) { brw_reg offset = build_lane_offsets(bld, spill_offset, ip); @@ -995,7 +995,7 @@ brw_reg_alloc::set_spill_costs() * spill/unspill we'll have to do, and guess that the insides of * loops run 10 times. */ - foreach_block_and_inst(block, fs_inst, inst, fs->cfg) { + foreach_block_and_inst(block, brw_inst, inst, fs->cfg) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == VGRF) spill_costs[inst->src[i].nr] += regs_read(devinfo, inst, i) * block_scale; @@ -1137,7 +1137,7 @@ brw_reg_alloc::spill_reg(unsigned spill_reg) * could just spill/unspill the GRF being accessed. */ int ip = 0; - foreach_block_and_inst (block, fs_inst, inst, fs->cfg) { + foreach_block_and_inst (block, brw_inst, inst, fs->cfg) { const brw_builder ibld = brw_builder(fs, block, inst); exec_node *before = inst->prev; exec_node *after = inst->next; @@ -1243,8 +1243,8 @@ brw_reg_alloc::spill_reg(unsigned spill_reg) subset_spill_offset, regs_written(inst), ip); } - for (fs_inst *inst = (fs_inst *)before->next; - inst != after; inst = (fs_inst *)inst->next) + for (brw_inst *inst = (brw_inst *)before->next; + inst != after; inst = (brw_inst *)inst->next) setup_inst_interference(inst); /* We don't advance the ip for scratch read/write instructions @@ -1320,7 +1320,7 @@ brw_reg_alloc::assign_regs(bool allow_spilling, bool spill_all) reg_unit(devinfo))); } - foreach_block_and_inst(block, fs_inst, inst, fs->cfg) { + foreach_block_and_inst(block, brw_inst, inst, fs->cfg) { assign_reg(devinfo, hw_reg_mapping, &inst->dst); for (int i = 0; i < inst->sources; i++) { assign_reg(devinfo, hw_reg_mapping, &inst->src[i]); diff --git a/src/intel/compiler/brw_schedule_instructions.cpp b/src/intel/compiler/brw_schedule_instructions.cpp index 41b0dd77e3c..1e5071b911f 100644 --- a/src/intel/compiler/brw_schedule_instructions.cpp +++ b/src/intel/compiler/brw_schedule_instructions.cpp @@ -64,7 +64,7 @@ class schedule_node : public exec_node public: void set_latency(const struct brw_isa_info *isa); - fs_inst *inst; + brw_inst *inst; schedule_node_child *children; int children_count; int children_cap; @@ -597,16 +597,16 @@ public: void update_children(schedule_node *chosen); void calculate_deps(); - bool is_compressed(const fs_inst *inst); + bool is_compressed(const brw_inst *inst); bool register_needs_barrier(const brw_reg ®); bool address_register_interfere(const schedule_node *n); schedule_node *choose_instruction_to_schedule(); - int calculate_issue_time(const fs_inst *inst); + int calculate_issue_time(const brw_inst *inst); - void count_reads_remaining(const fs_inst *inst); + void count_reads_remaining(const brw_inst *inst); void setup_liveness(cfg_t *cfg); - void update_register_pressure(const fs_inst *inst); - int get_register_pressure_benefit(const fs_inst *inst); + void update_register_pressure(const brw_inst *inst); + int get_register_pressure_benefit(const brw_inst *inst); void clear_last_grf_write(); void schedule_instructions(); @@ -717,7 +717,7 @@ brw_instruction_scheduler::brw_instruction_scheduler(void *mem_ctx, const fs_vis const struct brw_isa_info *isa = &s->compiler->isa; schedule_node *n = nodes; - foreach_block_and_inst(block, fs_inst, inst, s->cfg) { + foreach_block_and_inst(block, brw_inst, inst, s->cfg) { n->inst = inst; if (!post_reg_alloc) @@ -789,7 +789,7 @@ brw_instruction_scheduler::brw_instruction_scheduler(void *mem_ctx, const fs_vis } static bool -is_src_duplicate(const fs_inst *inst, int src) +is_src_duplicate(const brw_inst *inst, int src) { for (int i = 0; i < src; i++) if (inst->src[i].equals(inst->src[src])) @@ -799,7 +799,7 @@ is_src_duplicate(const fs_inst *inst, int src) } void -brw_instruction_scheduler::count_reads_remaining(const fs_inst *inst) +brw_instruction_scheduler::count_reads_remaining(const brw_inst *inst) { assert(reads_remaining); @@ -880,7 +880,7 @@ brw_instruction_scheduler::setup_liveness(cfg_t *cfg) } void -brw_instruction_scheduler::update_register_pressure(const fs_inst *inst) +brw_instruction_scheduler::update_register_pressure(const brw_inst *inst) { assert(reads_remaining); @@ -903,7 +903,7 @@ brw_instruction_scheduler::update_register_pressure(const fs_inst *inst) } int -brw_instruction_scheduler::get_register_pressure_benefit(const fs_inst *inst) +brw_instruction_scheduler::get_register_pressure_benefit(const brw_inst *inst) { int benefit = 0; const int block_idx = current.block->num; @@ -1081,7 +1081,7 @@ brw_instruction_scheduler::add_address_dep(schedule_node *before, schedule_node } static bool -is_scheduling_barrier(const fs_inst *inst) +is_scheduling_barrier(const brw_inst *inst) { return inst->opcode == SHADER_OPCODE_HALT_TARGET || inst->is_control_flow() || @@ -1089,7 +1089,7 @@ is_scheduling_barrier(const fs_inst *inst) } static bool -has_cross_lane_access(const fs_inst *inst) +has_cross_lane_access(const brw_inst *inst) { /* FINISHME: * @@ -1178,7 +1178,7 @@ void brw_instruction_scheduler::add_cross_lane_deps(schedule_node *n) { for (schedule_node *prev = n - 1; prev >= current.start; prev--) { - if (has_cross_lane_access((fs_inst*)prev->inst)) + if (has_cross_lane_access((brw_inst*)prev->inst)) add_dep(prev, n, 0); } } @@ -1187,7 +1187,7 @@ brw_instruction_scheduler::add_cross_lane_deps(schedule_node *n) * actually writes 2 MRFs. */ bool -brw_instruction_scheduler::is_compressed(const fs_inst *inst) +brw_instruction_scheduler::is_compressed(const brw_inst *inst) { return inst->exec_size == 16; } @@ -1208,7 +1208,7 @@ brw_instruction_scheduler::clear_last_grf_write() { if (!post_reg_alloc) { for (schedule_node *n = current.start; n < current.end; n++) { - fs_inst *inst = (fs_inst *)n->inst; + brw_inst *inst = n->inst; if (inst->dst.file == VGRF) { /* Don't bother being careful with regs_written(), quicker to just clear 2 cachelines. */ @@ -1289,7 +1289,7 @@ brw_instruction_scheduler::calculate_deps() * (like the accumulator, flag, etc...). */ for (schedule_node *n = current.start; n < current.end; n++) { - fs_inst *inst = (fs_inst *)n->inst; + brw_inst *inst = n->inst; /* Pre pass going over instruction using the register flag as a * source. @@ -1316,7 +1316,7 @@ brw_instruction_scheduler::calculate_deps() } for (schedule_node *n = current.start; n < current.end; n++) { - fs_inst *inst = (fs_inst *)n->inst; + brw_inst *inst = n->inst; if (is_scheduling_barrier(inst)) add_barrier_deps(n); @@ -1427,7 +1427,7 @@ brw_instruction_scheduler::calculate_deps() memset(last_address_write, 0, sizeof(last_address_write)); for (schedule_node *n = current.end - 1; n >= current.start; n--) { - fs_inst *inst = (fs_inst *)n->inst; + brw_inst *inst = n->inst; /* write-after-read deps. */ for (int i = 0; i < inst->sources; i++) { @@ -1657,7 +1657,7 @@ brw_instruction_scheduler::choose_instruction_to_schedule() } int -brw_instruction_scheduler::calculate_issue_time(const fs_inst *inst) +brw_instruction_scheduler::calculate_issue_time(const brw_inst *inst) { const struct brw_isa_info *isa = &s->compiler->isa; const unsigned overhead = s->grf_used && has_bank_conflict(isa, inst) ? diff --git a/src/intel/compiler/brw_validate.cpp b/src/intel/compiler/brw_validate.cpp index 03fea3e8c22..91092dfaddd 100644 --- a/src/intel/compiler/brw_validate.cpp +++ b/src/intel/compiler/brw_validate.cpp @@ -95,7 +95,7 @@ is_ud_imm(const brw_reg ®) } static void -validate_memory_logical(const fs_visitor &s, const fs_inst *inst) +validate_memory_logical(const fs_visitor &s, const brw_inst *inst) { const intel_device_info *devinfo = s.devinfo; @@ -200,7 +200,7 @@ brw_shader_phase_to_string(enum brw_shader_phase phase) } static void -brw_validate_instruction_phase(const fs_visitor &s, fs_inst *inst) +brw_validate_instruction_phase(const fs_visitor &s, brw_inst *inst) { enum brw_shader_phase invalid_from = BRW_SHADER_PHASE_INVALID; @@ -291,7 +291,7 @@ brw_validate(const fs_visitor &s) */ uint32_t last_used_address_register[16] = {}; - foreach_inst_in_block (fs_inst, inst, block) { + foreach_inst_in_block (brw_inst, inst, block) { brw_validate_instruction_phase(s, inst); switch (inst->opcode) { diff --git a/src/intel/compiler/brw_workaround.cpp b/src/intel/compiler/brw_workaround.cpp index 75bbf578459..c267eff0a8d 100644 --- a/src/intel/compiler/brw_workaround.cpp +++ b/src/intel/compiler/brw_workaround.cpp @@ -19,7 +19,7 @@ brw_workaround_emit_dummy_mov_instruction(fs_visitor &s) if (!intel_needs_workaround(s.devinfo, 14015360517)) return false; - fs_inst *first_inst = + brw_inst *first_inst = s.cfg->first_block()->start(); /* We can skip the WA if first instruction is marked with @@ -31,7 +31,7 @@ brw_workaround_emit_dummy_mov_instruction(fs_visitor &s) /* Insert dummy mov as first instruction. */ const brw_builder ubld = - brw_builder(&s, s.cfg->first_block(), (fs_inst *)first_inst).exec_all().group(8, 0); + brw_builder(&s, s.cfg->first_block(), (brw_inst *)first_inst).exec_all().group(8, 0); ubld.MOV(ubld.null_reg_ud(), brw_imm_ud(0u)); s.invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES); @@ -39,7 +39,7 @@ brw_workaround_emit_dummy_mov_instruction(fs_visitor &s) } static bool -needs_dummy_fence(const intel_device_info *devinfo, fs_inst *inst) +needs_dummy_fence(const intel_device_info *devinfo, brw_inst *inst) { /* This workaround is about making sure that any instruction writing * through UGM has completed before we hit EOT. @@ -90,7 +90,7 @@ brw_workaround_memory_fence_before_eot(fs_visitor &s) if (!intel_needs_workaround(s.devinfo, 22013689345)) return false; - foreach_block_and_inst_safe (block, fs_inst, inst, s.cfg) { + foreach_block_and_inst_safe (block, brw_inst, inst, s.cfg) { if (!inst->eot) { if (needs_dummy_fence(s.devinfo, inst)) has_ugm_write_or_atomic = true; @@ -104,7 +104,7 @@ brw_workaround_memory_fence_before_eot(fs_visitor &s) const brw_builder ubld = ibld.exec_all().group(1, 0); brw_reg dst = ubld.vgrf(BRW_TYPE_UD); - fs_inst *dummy_fence = ubld.emit(SHADER_OPCODE_MEMORY_FENCE, + brw_inst *dummy_fence = ubld.emit(SHADER_OPCODE_MEMORY_FENCE, dst, brw_vec8_grf(0, 0), /* commit enable */ brw_imm_ud(1), /* bti */ brw_imm_ud(0)); @@ -131,10 +131,10 @@ brw_workaround_memory_fence_before_eot(fs_visitor &s) * find_halt_control_flow_region_end(), the region of divergence extends until * the only SHADER_OPCODE_HALT_TARGET in the program. */ -static const fs_inst * +static const brw_inst * find_halt_control_flow_region_start(const fs_visitor *v) { - foreach_block_and_inst(block, fs_inst, inst, v->cfg) { + foreach_block_and_inst(block, brw_inst, inst, v->cfg) { if (inst->opcode == BRW_OPCODE_HALT || inst->opcode == SHADER_OPCODE_HALT_TARGET) return inst; @@ -164,7 +164,7 @@ brw_workaround_nomask_control_flow(fs_visitor &s) const brw_predicate pred = s.dispatch_width > 16 ? BRW_PREDICATE_ALIGN1_ANY32H : s.dispatch_width > 8 ? BRW_PREDICATE_ALIGN1_ANY16H : BRW_PREDICATE_ALIGN1_ANY8H; - const fs_inst *halt_start = find_halt_control_flow_region_start(&s); + const brw_inst *halt_start = find_halt_control_flow_region_start(&s); unsigned depth = 0; bool progress = false; @@ -178,7 +178,7 @@ brw_workaround_nomask_control_flow(fs_visitor &s) .flag_liveout[0]; STATIC_ASSERT(ARRAY_SIZE(live_vars.block_data[0].flag_liveout) == 1); - foreach_inst_in_block_reverse_safe(fs_inst, inst, block) { + foreach_inst_in_block_reverse_safe(brw_inst, inst, block) { if (!inst->predicate && inst->exec_size >= 8) flag_liveout &= ~inst->flags_written(s.devinfo); @@ -311,7 +311,7 @@ brw_workaround_source_arf_before_eot(fs_visitor &s) foreach_block(block, s.cfg) { unsigned flags_unread_in_block = 0; - foreach_inst_in_block(fs_inst, inst, block) { + foreach_inst_in_block(brw_inst, inst, block) { /* Instruction can read and write to the same flag, so the order is important */ flags_unread_in_block &= ~bytes_bitmask_to_words(inst->flags_read(s.devinfo)); flags_unread_in_block |= bytes_bitmask_to_words(inst->flags_written(s.devinfo)); @@ -333,7 +333,7 @@ brw_workaround_source_arf_before_eot(fs_visitor &s) if (flags_unread) { int eot_count = 0; - foreach_block_and_inst_safe(block, fs_inst, inst, s.cfg) + foreach_block_and_inst_safe(block, brw_inst, inst, s.cfg) { if (!inst->eot) continue; diff --git a/src/intel/compiler/test_lower_scoreboard.cpp b/src/intel/compiler/test_lower_scoreboard.cpp index d8eae852359..a7c7cc0db50 100644 --- a/src/intel/compiler/test_lower_scoreboard.cpp +++ b/src/intel/compiler/test_lower_scoreboard.cpp @@ -77,12 +77,12 @@ scoreboard_test::~scoreboard_test() ctx = NULL; } -static fs_inst * +static brw_inst * instruction(bblock_t *block, int num) { - fs_inst *inst = (fs_inst *)block->start(); + brw_inst *inst = (brw_inst *)block->start(); for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; + inst = (brw_inst *)inst->next; } return inst; } @@ -105,11 +105,11 @@ lower_scoreboard(fs_visitor *v) } } -fs_inst * +brw_inst * emit_SEND(const brw_builder &bld, const brw_reg &dst, const brw_reg &desc, const brw_reg &payload) { - fs_inst *inst = bld.emit(SHADER_OPCODE_SEND, dst, desc, desc, payload); + brw_inst *inst = bld.emit(SHADER_OPCODE_SEND, dst, desc, desc, payload); inst->mlen = 1; return inst; } @@ -265,7 +265,7 @@ TEST_F(scoreboard_test, RAW_outoforder_outoforder) EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - fs_inst *sync = instruction(block0, 1); + brw_inst *sync = instruction(block0, 1); EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC); EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_DST, 0)); @@ -375,7 +375,7 @@ TEST_F(scoreboard_test, WAR_outoforder_outoforder) EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - fs_inst *sync = instruction(block0, 1); + brw_inst *sync = instruction(block0, 1); EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC); EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_SRC, 0)); @@ -490,7 +490,7 @@ TEST_F(scoreboard_test, WAW_outoforder_outoforder) EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - fs_inst *sync = instruction(block0, 1); + brw_inst *sync = instruction(block0, 1); EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC); EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_DST, 0)); @@ -518,12 +518,12 @@ TEST_F(scoreboard_test, loop1) lower_scoreboard(v); bblock_t *body = v->cfg->blocks[2]; - fs_inst *add = instruction(body, 0); + brw_inst *add = instruction(body, 0); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 1)); bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 0); + brw_inst *mul = instruction(last_block, 0); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 1)); } @@ -553,12 +553,12 @@ TEST_F(scoreboard_test, loop2) /* Now the write in ADD has the tightest RegDist for both ADD and MUL. */ bblock_t *body = v->cfg->blocks[2]; - fs_inst *add = instruction(body, 0); + brw_inst *add = instruction(body, 0); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 2)); bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 0); + brw_inst *mul = instruction(last_block, 0); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 2)); } @@ -589,12 +589,12 @@ TEST_F(scoreboard_test, loop3) lower_scoreboard(v); bblock_t *body = v->cfg->blocks[2]; - fs_inst *add = instruction(body, 4); + brw_inst *add = instruction(body, 4); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 5)); bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 0); + brw_inst *mul = instruction(last_block, 0); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 1)); } @@ -619,12 +619,12 @@ TEST_F(scoreboard_test, conditional1) lower_scoreboard(v); bblock_t *body = v->cfg->blocks[1]; - fs_inst *add = instruction(body, 0); + brw_inst *add = instruction(body, 0); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 2)); bblock_t *last_block = v->cfg->blocks[2]; - fs_inst *mul = instruction(last_block, 1); + brw_inst *mul = instruction(last_block, 1); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 2)); } @@ -651,12 +651,12 @@ TEST_F(scoreboard_test, conditional2) lower_scoreboard(v); bblock_t *body = v->cfg->blocks[1]; - fs_inst *add = instruction(body, 0); + brw_inst *add = instruction(body, 0); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 5)); bblock_t *last_block = v->cfg->blocks[2]; - fs_inst *mul = instruction(last_block, 1); + brw_inst *mul = instruction(last_block, 1); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 2)); } @@ -683,12 +683,12 @@ TEST_F(scoreboard_test, conditional3) lower_scoreboard(v); bblock_t *body = v->cfg->blocks[1]; - fs_inst *add = instruction(body, 3); + brw_inst *add = instruction(body, 3); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 5)); bblock_t *last_block = v->cfg->blocks[2]; - fs_inst *mul = instruction(last_block, 1); + brw_inst *mul = instruction(last_block, 1); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 2)); } @@ -715,12 +715,12 @@ TEST_F(scoreboard_test, conditional4) lower_scoreboard(v); bblock_t *body = v->cfg->blocks[1]; - fs_inst *add = instruction(body, 0); + brw_inst *add = instruction(body, 0); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 2)); bblock_t *last_block = v->cfg->blocks[2]; - fs_inst *mul = instruction(last_block, 1); + brw_inst *mul = instruction(last_block, 1); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 3)); } @@ -747,17 +747,17 @@ TEST_F(scoreboard_test, conditional5) lower_scoreboard(v); bblock_t *then_body = v->cfg->blocks[1]; - fs_inst *add = instruction(then_body, 0); + brw_inst *add = instruction(then_body, 0); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 2)); bblock_t *else_body = v->cfg->blocks[2]; - fs_inst *rol = instruction(else_body, 0); + brw_inst *rol = instruction(else_body, 0); EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL); EXPECT_EQ(rol->sched, regdist(TGL_PIPE_FLOAT, 2)); bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 1); + brw_inst *mul = instruction(last_block, 1); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 2)); } @@ -791,17 +791,17 @@ TEST_F(scoreboard_test, conditional6) lower_scoreboard(v); bblock_t *then_body = v->cfg->blocks[1]; - fs_inst *add = instruction(then_body, 3); + brw_inst *add = instruction(then_body, 3); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 5)); bblock_t *else_body = v->cfg->blocks[2]; - fs_inst *rol = instruction(else_body, 4); + brw_inst *rol = instruction(else_body, 4); EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL); EXPECT_EQ(rol->sched, regdist(TGL_PIPE_FLOAT, 6)); bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 1); + brw_inst *mul = instruction(last_block, 1); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 2)); } @@ -835,17 +835,17 @@ TEST_F(scoreboard_test, conditional7) lower_scoreboard(v); bblock_t *then_body = v->cfg->blocks[1]; - fs_inst *add = instruction(then_body, 0); + brw_inst *add = instruction(then_body, 0); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 2)); bblock_t *else_body = v->cfg->blocks[2]; - fs_inst *rol = instruction(else_body, 0); + brw_inst *rol = instruction(else_body, 0); EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL); EXPECT_EQ(rol->sched, regdist(TGL_PIPE_FLOAT, 2)); bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 1); + brw_inst *mul = instruction(last_block, 1); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 6)); } @@ -877,7 +877,7 @@ TEST_F(scoreboard_test, conditional8) lower_scoreboard(v); bblock_t *then_body = v->cfg->blocks[1]; - fs_inst *add = instruction(then_body, 0); + brw_inst *add = instruction(then_body, 0); EXPECT_EQ(add->opcode, BRW_OPCODE_ADD); EXPECT_EQ(add->sched, regdist(TGL_PIPE_FLOAT, 7)); @@ -885,12 +885,12 @@ TEST_F(scoreboard_test, conditional8) * physical CFG edge between the then-block and the else-block. */ bblock_t *else_body = v->cfg->blocks[2]; - fs_inst *rol = instruction(else_body, 0); + brw_inst *rol = instruction(else_body, 0); EXPECT_EQ(rol->opcode, BRW_OPCODE_ROL); EXPECT_EQ(rol->sched, regdist(TGL_PIPE_FLOAT, 2)); bblock_t *last_block = v->cfg->blocks[3]; - fs_inst *mul = instruction(last_block, 1); + brw_inst *mul = instruction(last_block, 1); EXPECT_EQ(mul->opcode, BRW_OPCODE_MUL); EXPECT_EQ(mul->sched, regdist(TGL_PIPE_FLOAT, 2)); } @@ -1144,7 +1144,7 @@ TEST_F(scoreboard_test, gfx200_cannot_embed_outoforder_src_dependency_in_send_eo EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - fs_inst *sync = instruction(block0, 1); + brw_inst *sync = instruction(block0, 1); EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC); EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_SRC, 0)); @@ -1175,7 +1175,7 @@ TEST_F(scoreboard_test, gfx200_cannot_embed_outoforder_dst_dependency_in_send_eo EXPECT_EQ(instruction(block0, 0)->sched, tgl_swsb_sbid(TGL_SBID_SET, 0)); - fs_inst *sync = instruction(block0, 1); + brw_inst *sync = instruction(block0, 1); EXPECT_EQ(sync->opcode, BRW_OPCODE_SYNC); EXPECT_EQ(sync->sched, tgl_swsb_sbid(TGL_SBID_DST, 0)); diff --git a/src/intel/compiler/test_opt_cmod_propagation.cpp b/src/intel/compiler/test_opt_cmod_propagation.cpp index 0e796a3caa8..f02b430d506 100644 --- a/src/intel/compiler/test_opt_cmod_propagation.cpp +++ b/src/intel/compiler/test_opt_cmod_propagation.cpp @@ -87,12 +87,12 @@ cmod_propagation_test::~cmod_propagation_test() ctx = NULL; } -static fs_inst * +static brw_inst * instruction(bblock_t *block, int num) { - fs_inst *inst = (fs_inst *)block->start(); + brw_inst *inst = (brw_inst *)block->start(); for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; + inst = (brw_inst *)inst->next; } return inst; } diff --git a/src/intel/compiler/test_opt_copy_propagation.cpp b/src/intel/compiler/test_opt_copy_propagation.cpp index 177e829b090..2e9e6d4357a 100644 --- a/src/intel/compiler/test_opt_copy_propagation.cpp +++ b/src/intel/compiler/test_opt_copy_propagation.cpp @@ -76,12 +76,12 @@ copy_propagation_test::~copy_propagation_test() ctx = NULL; } -static fs_inst * +static brw_inst * instruction(bblock_t *block, int num) { - fs_inst *inst = (fs_inst *)block->start(); + brw_inst *inst = (brw_inst *)block->start(); for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; + inst = (brw_inst *)inst->next; } return inst; } @@ -135,12 +135,12 @@ TEST_F(copy_propagation_test, basic) EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - fs_inst *mov = instruction(block0, 0); + brw_inst *mov = instruction(block0, 0); EXPECT_EQ(BRW_OPCODE_MOV, mov->opcode); EXPECT_TRUE(mov->dst.equals(vgrf0)); EXPECT_TRUE(mov->src[0].equals(vgrf2)); - fs_inst *add = instruction(block0, 1); + brw_inst *add = instruction(block0, 1); EXPECT_EQ(BRW_OPCODE_ADD, add->opcode); EXPECT_TRUE(add->dst.equals(vgrf1)); EXPECT_TRUE(add->src[0].equals(vgrf2)); @@ -181,8 +181,8 @@ TEST_F(copy_propagation_test, maxmax_sat_imm) }; for (unsigned i = 0; i < sizeof(test) / sizeof(test[0]); i++) { - fs_inst *mov = set_saturate(true, bld.MOV(vgrf0, vgrf1)); - fs_inst *sel = set_condmod(test[i].conditional_mod, + brw_inst *mov = set_saturate(true, bld.MOV(vgrf0, vgrf1)); + brw_inst *sel = set_condmod(test[i].conditional_mod, bld.SEL(vgrf2, vgrf0, brw_imm_f(test[i].immediate))); @@ -249,12 +249,12 @@ TEST_F(copy_propagation_test, mixed_integer_sign) EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - fs_inst *mov = instruction(block0, 0); + brw_inst *mov = instruction(block0, 0); EXPECT_EQ(BRW_OPCODE_MOV, mov->opcode); EXPECT_TRUE(mov->dst.equals(vgrf1)); EXPECT_TRUE(mov->src[0].equals(vgrf0)); - fs_inst *bfe = instruction(block0, 1); + brw_inst *bfe = instruction(block0, 1); EXPECT_EQ(BRW_OPCODE_BFE, bfe->opcode); EXPECT_TRUE(bfe->dst.equals(vgrf2)); EXPECT_TRUE(bfe->src[0].equals(vgrf3)); @@ -292,12 +292,12 @@ TEST_F(copy_propagation_test, mixed_integer_sign_with_vector_imm) EXPECT_EQ(0, block0->start_ip); EXPECT_EQ(1, block0->end_ip); - fs_inst *mov = instruction(block0, 0); + brw_inst *mov = instruction(block0, 0); EXPECT_EQ(BRW_OPCODE_MOV, mov->opcode); EXPECT_TRUE(mov->dst.equals(vgrf0)); EXPECT_TRUE(mov->src[0].file == IMM); - fs_inst *add = instruction(block0, 1); + brw_inst *add = instruction(block0, 1); EXPECT_EQ(BRW_OPCODE_ADD, add->opcode); EXPECT_TRUE(add->dst.equals(vgrf1)); EXPECT_TRUE(add->src[0].equals(vgrf2)); diff --git a/src/intel/compiler/test_opt_cse.cpp b/src/intel/compiler/test_opt_cse.cpp index f163515c8b7..9e47eabd3d0 100644 --- a/src/intel/compiler/test_opt_cse.cpp +++ b/src/intel/compiler/test_opt_cse.cpp @@ -59,12 +59,12 @@ cse_test::~cse_test() } -static fs_inst * +static brw_inst * instruction(bblock_t *block, int num) { - fs_inst *inst = (fs_inst *)block->start(); + brw_inst *inst = (brw_inst *)block->start(); for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; + inst = (brw_inst *)inst->next; } return inst; } diff --git a/src/intel/compiler/test_opt_saturate_propagation.cpp b/src/intel/compiler/test_opt_saturate_propagation.cpp index fc034e9a439..7bac9f020db 100644 --- a/src/intel/compiler/test_opt_saturate_propagation.cpp +++ b/src/intel/compiler/test_opt_saturate_propagation.cpp @@ -77,12 +77,12 @@ saturate_propagation_test::~saturate_propagation_test() } -static fs_inst * +static brw_inst * instruction(bblock_t *block, int num) { - fs_inst *inst = (fs_inst *)block->start(); + brw_inst *inst = (brw_inst *)block->start(); for (int i = 0; i < num; i++) { - inst = (fs_inst *)inst->next; + inst = (brw_inst *)inst->next; } return inst; } @@ -395,7 +395,7 @@ TEST_F(saturate_propagation_test, mad_imm_float_neg_mov_sat) /* The builder for MAD tries to be helpful and not put immediates as direct * sources. We want to test specifically that case. */ - fs_inst *mad = bld.MAD(dst0, src2, src2, src2); + brw_inst *mad = bld.MAD(dst0, src2, src2, src2); mad->src[0] = brw_imm_f(1.0f); mad->src[1] = brw_imm_f(-2.0f); dst0.negate = true;