From d4086be6bcd7624a4d2bafad065aa94e9c27486a Mon Sep 17 00:00:00 2001
From: M Henning <drawoc@darkrefraction.com>
Date: Thu, 20 Jul 2023 22:54:52 -0400
Subject: [PATCH] nv/codegen: Implement nir_op_fquantize2f16

Passes most of dEQP-VK.spirv_assembly.instruction.graphics.opquantize.* but
not the too_small_* tests for some reason. (Tested on kepler.)

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24327>
---
 src/nouveau/codegen/nv50_ir_from_nir.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp
index e0eeaebe7d6..b2041899714 100644
--- a/src/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -2838,6 +2838,14 @@ Converter::visit(nir_alu_instr *insn)
       mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0));
       break;
    }
+   case nir_op_fquantize2f16: {
+      DEFAULT_CHECKS;
+      LValues &newDefs = convert(&insn->dest);
+      Value *tmp = getSSA();
+      mkCvt(OP_CVT, TYPE_F16, tmp, TYPE_F32, getSrc(&insn->src[0]))->ftz = 1;
+      mkCvt(OP_CVT, TYPE_F32, newDefs[0], TYPE_F16, tmp);
+      break;
+   }
    case nir_op_urol: {
       DEFAULT_CHECKS;
       LValues &newDefs = convert(&insn->dest);