From d37241bdc4fb23139793b135a00036de496cf9f2 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Tue, 9 Mar 2021 09:19:45 +0100 Subject: [PATCH] broadcom/compiler: move code block around MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These checks depend on prev_inst being set, so move them down below with all the other checks with the same requirement. Reviewed-by: Alejandro Piñeiro Part-of: --- src/broadcom/compiler/qpu_schedule.c | 31 ++++++++++++++-------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/src/broadcom/compiler/qpu_schedule.c b/src/broadcom/compiler/qpu_schedule.c index 9283b936ccc..7f6ac5af0b4 100644 --- a/src/broadcom/compiler/qpu_schedule.c +++ b/src/broadcom/compiler/qpu_schedule.c @@ -903,21 +903,6 @@ choose_instruction_to_schedule(struct v3d_compile *c, const struct v3d_qpu_instr *inst = &n->inst->qpu; - /* Simulator complains if we have two uniforms loaded in the - * the same instruction, which could happen if we have a ldunif - * or sideband uniform and we pair that with ldunifa. - */ - if (prev_inst) { - if (vir_has_uniform(prev_inst->inst) && - (inst->sig.ldunifa || inst->sig.ldunifarf)) { - continue; - } - if ((prev_inst->inst->qpu.sig.ldunifa || - prev_inst->inst->qpu.sig.ldunifarf) && - vir_has_uniform(n->inst)) { - continue; - } - } /* Don't choose the branch instruction until it's the last one * left. We'll move it up to fit its delay slots after we @@ -977,6 +962,22 @@ choose_instruction_to_schedule(struct v3d_compile *c, n->inst->uniform != -1) continue; + /* Simulator complains if we have two uniforms loaded in + * the the same instruction, which could happen if we + * have a ldunif or sideband uniform and we pair that + * with ldunifa. + */ + if (vir_has_uniform(prev_inst->inst) && + (inst->sig.ldunifa || inst->sig.ldunifarf)) { + continue; + } + + if ((prev_inst->inst->qpu.sig.ldunifa || + prev_inst->inst->qpu.sig.ldunifarf) && + vir_has_uniform(n->inst)) { + continue; + } + /* Don't merge in something that will lock the TLB. * Hopwefully what we have in inst will release some * other instructions, allowing us to delay the