diff --git a/src/freedreno/vulkan/tu_clear_blit.cc b/src/freedreno/vulkan/tu_clear_blit.cc
index 6b9ba78d13b..25c24b98ca8 100644
--- a/src/freedreno/vulkan/tu_clear_blit.cc
+++ b/src/freedreno/vulkan/tu_clear_blit.cc
@@ -1648,7 +1648,7 @@ r3d_setup(struct tu_cmd_buffer *cmd,
       tu_cs_emit_regs(cs, GRAS_LRZ_DEPTH_BUFFER_INFO(CHIP));
 
       tu_cs_emit_regs(cs, A6XX_RB_VRS_CONFIG());
-      tu_cs_emit_regs(cs, A7XX_SP_VRS_CONFIG());
+      tu_cs_emit_regs(cs, SP_VRS_CONFIG(CHIP));
       tu_cs_emit_regs(cs, GRAS_VRS_CONFIG(CHIP));
    }
 
diff --git a/src/freedreno/vulkan/tu_pipeline.cc b/src/freedreno/vulkan/tu_pipeline.cc
index 6c2c6ba3fc7..d1059b2cf71 100644
--- a/src/freedreno/vulkan/tu_pipeline.cc
+++ b/src/freedreno/vulkan/tu_pipeline.cc
@@ -3612,7 +3612,7 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs,
     */
    if (!fsr || (!fs_reads_fsr && vk_fragment_shading_rate_is_disabled(fsr))) {
       tu_cs_emit_regs(cs, A6XX_RB_VRS_CONFIG());
-      tu_cs_emit_regs(cs, A7XX_SP_VRS_CONFIG());
+      tu_cs_emit_regs(cs, SP_VRS_CONFIG(CHIP));
       tu_cs_emit_regs(cs, GRAS_VRS_CONFIG(CHIP));
       return;
    }
@@ -3646,10 +3646,10 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs,
       A6XX_RB_VRS_CONFIG(.unk2 = true, .pipeline_fsr_enable = enable_draw_fsr,
                          .attachment_fsr_enable = enable_att_fsr,
                          .primitive_fsr_enable = enable_prim_fsr));
-   tu_cs_emit_regs(
-      cs, A7XX_SP_VRS_CONFIG(.pipeline_fsr_enable = enable_draw_fsr,
-                             .attachment_fsr_enable = enable_att_fsr,
-                             .primitive_fsr_enable = enable_prim_fsr));
+   tu_cs_emit_regs(cs,
+                   SP_VRS_CONFIG(CHIP, .pipeline_fsr_enable = enable_draw_fsr,
+                                 .attachment_fsr_enable = enable_att_fsr,
+                                 .primitive_fsr_enable = enable_prim_fsr));
    tu_cs_emit_regs(
       cs, GRAS_VRS_CONFIG(CHIP,
                 .pipeline_fsr_enable = enable_draw_fsr,